參數(shù)資料
型號： OR4E10
廠商： Lineage Power
英文描述： Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列)
中文描述： 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列）
文件頁數(shù)： 61/132頁
文件大?。?/td> 2667K
代理商： OR4E10
Lucent Technologies Inc.
61
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
FPGA States of Operation
(continued)
Table 36A. Configuration Frame Format and Contents
Table 36B. Configuration Frame Format and Contents for Embedded Block RAM
Frame
Contents
11110010
24-bit length count
11111111
0101 1111 1111 1111
44 reserved bits
Part ID
Checksum
11111111
1111 0010
11111111
00
14-bit address
Checksum
11111111
01
Alignment bits
Data bits
Checksum
11111111
00 or 10
11111111 111111
11111111 11111111
Description
Header
Preamble for generic FPGA.
Configuration bit stream length.
8-bit trailing header.
ID frame header.
Reserved bits set to 0.
20-bit part ID.
8-bit checksum.
8 stop bits (high) to separate frames.
This is a new mandatory header for generic portion.
8 stop bits (high) to separate frames.
Address frame header.
14-bit address of generic FPGA.
8-bit checksum.
Eight stop bits (high) to separate frames.
Data frame header, same as generic.
String of 0 bits added to frame to reach a byte boundary.
Number of data bits depends upon device.
8-bit checksum.
Eight stop bits (high) to separate frames.
Postamble header, 00 = finish, 10 = more bits coming.
Dummy address.
16 stop bits (high).
ID Frame
FPGA Header
FPGA
Address
Frame
FPGA
Data Frame
Postamble
for Generic
FPGA
Frame
Contents
11110001
11111111
00
6-bit address
Checksum
11111111
01
000000
512x18 data bits
Checksum
11111111
00 or 10
111111
11111111 11111111
Description
RAM Header
A mandatory header for RAM bit stream portion.
8 stop bits (high) to separate frames.
Address frame header, same as generic.
6-bit address of RAM blocks.
8-bit checksum.
Eight stop bits (high) to separate frames.
Data frame header. same as generic.
Six of 0 bits added to reach a byte boundary.
Exact number of bits in a RAM block.
8-bit checksum.
Eight stop bits (high) to separate frames.
Postamble header. 00 = finish, 10 = more bits coming.
Dummy address.
16 stop bits (high).
RAM
Address
Frame
RAM
Data Frame
Postamble
for RAM
相關(guān)PDF資料
PDF描述
OR4E14 Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列)
OR4E2 Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR4E14 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays
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OR4E2-1BA256 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
OR4E2-1BA352 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
OR4E2-1BA416 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
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