參數(shù)資料
型號: OR4E10
廠商: Lineage Power
英文描述: Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列)
中文描述: 現(xiàn)場可編程門陣列(現(xiàn)場可編程門陣列)
文件頁數(shù): 29/132頁
文件大小: 2667K
代理商: OR4E10
Lucent Technologies Inc.
29
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Embedded Block RAM
(continued)
0308 (F)
Figure 21. EBR Read and Write Cycles with Write Through
Table 10. FIFO Signals
Port Signals
AR(1:0)[9:0]
AW(1:0)[9:0]
FF
PFF
PEF
EF
D0[17:0]
D1[17:0]
CKW[0:1]
CKR[0:1]
CSW[1:0]
CSR[1:0]
RESET
Q0[17:0]
Q1[17:0]
I/O
I
I
O
O
O
O
I
I
I
I
I
I
I
O
O
Function
Programs FIFO flags. Used for partially empty flag size.
Programs FIFO flags. Used for partially full flag size.
Full flag.
Partially full flag.
Partially empty flag.
Empty flag.
Data inputs for all configurations.
Data inputs for 256 x 36 configurations only.
Positive-edge write port clock. Port 1 only used for 256 x 36 configurations.
Positive-edge read port clock. Port 1 only used for 256 x 36 configurations.
Active-high write enable. Port 1 only used for 256 x 36 configurations.
Active-high read enable. Port 1 only used for 256 x 36 configurations.
Active-low. Resets FIFO pointers.
Data outputs for all configurations.
Data outputs for 256 x 36 configurations.
CKWPH
CKWPL
CSWSU
CSWH
AWH
DSU
DH
BWSU
BWH
AWSU
CKWQ
AQ
AQH
a
b
c
d
b
c
a
d
c
CKW
CSW
AW
D
BW
AR
Q
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