參數(shù)資料
型號(hào): MT4LDT464AG
廠商: Micron Technology, Inc.
英文描述: 4 Meg x 64 Nonbuffered DRAM DIMMs(4 M x 64無(wú)緩沖動(dòng)態(tài)RAM雙列直插存儲(chǔ)器模塊)
中文描述: 4梅格× 64 Nonbuffered內(nèi)存插槽(4個(gè)M × 64無(wú)緩沖動(dòng)態(tài)RAM的雙列直插存儲(chǔ)器模塊)
文件頁(yè)數(shù): 12/31頁(yè)
文件大小: 439K
代理商: MT4LDT464AG
1, 2, 4 Meg x 64 Nonbuffered DRAM DIMMs
DM67.p65 – Rev. 6/98
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
12
1, 2, 4 MEG x 64
NONBUFFERED DRAM DIMMs
OBSOLETE
EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 29) (V
DD
= +3.3V
±
0.3V)
AC CHARACTERISTICS - EDO PAGE MODE OPTION
PARAMETER
Access time from column address
Column-address setup to CAS#
precharge during writes
Column-address hold time (referenced to RAS#)
Column-address setup time
Row-address setup time
Column-address to WE# delay time
Access time from CAS#
Column-address hold time
CAS# pulse width
CAS# hold time (CBR Refresh)
CAS# to output in Low-Z
Data output hold after CAS# LOW
CAS# precharge time
Access time from CAS# precharge
CAS# to RAS# precharge time
CAS# hold time
CAS# setup time (CBR Refresh)
CAS# to WE# delay time
WRITE command to CAS# lead time
Data-in hold time
Data-in setup time
Output disable
Output enable
OE# hold time from WE# during
READ-MODIFY-WRITE cycle
OE# HIGH hold time from CAS# HIGH
OE# HIGH pulse width
OE# LOW to CAS# HIGH setup time
Output buffer turn-off delay
OE# setup prior to RAS#
during HIDDEN REFRESH cycle
EDO-PAGE-MODE READ or WRITE cycle time
EDO-PAGE-MODE READ-WRITE cycle time
Access time from RAS#
RAS# to column-address delay time
Row-address hold time
RAS# pulse width
RAS# pulse width (EDO PAGE MODE)
Random READ or WRITE cycle time
RAS# to CAS# delay time
READ command hold time (referenced to CAS#)
READ command setup time
-5
-6
SYMBOL
t
AA
t
ACH
MIN
MAX
25
MIN
MAX
30
UNITS
ns
ns
NOTES
12
15
t
AR
t
ASC
t
ASR
t
AWD
t
CAC
t
CAH
t
CAS
t
CHR
t
CLZ
t
COH
t
CP
t
CPA
t
CRP
t
CSH
t
CSR
t
CWD
t
CWL
t
DH
t
DS
t
OD
t
OE
t
OEH
38
0
0
42
45
0
0
49
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
23
14
13/15*
15
8
8
8
0
3
8
10
10
10
0
3
10
10,000
10,000
4
15
28
35
5
5
38
5
28
8
8
0
0
45
5
35
10
10
0
0
4
23
22
22
12
12
15
15
8
10/12**
t
OEHC
t
OEP
t
OES
t
OFF
t
ORD
5
5
4
0
0
10
5
5
0
0
ns
ns
ns
ns
ns
12
15
19, 26
19
t
PC
20
47
25
56
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
PRWC
t
RAC
t
RAD
t
RAH
t
RAS
t
RASP
t
RC
t
RCD
t
RCH
t
RCS
50
60
13
17
9
9
12
10
60
60
104
14
0
0
50
50
84
11
0
0
10,000
125,000
10,000
125,000
16
18
* 8MB DIMM
**16MB DIMM
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