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參數(shù)資料
| 型號： | MT55V1MV18P |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 16Mb: 1 Meg x 18, Flow-Through ZBT SRAM(16Mb流通式同步靜態(tài)存儲器) |
| 中文描述： | 16Mb的：1梅格× 18，流量通過ZBT SRAM的（16Mb的流通式同步靜態(tài)存儲器） |
| 文件頁數(shù)： | 1/34頁 |
| 文件大小： | 460K |
| 代理商： | MT55V1MV18P |
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1
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1M18P_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
16Mb
ZBT
SRAM
FEATURES
High frequency and 100 percent bus utilization
Fast cycle times: 6ns, 7.5ns, and 10ns
Single +3.3V ±5% or +2.5V ±5% power supply
(V
DD
)
Separate +3.3V or +2.5V isolated output buffer
supply (V
DD
Q)
Advanced control logic for minimum control
signal interface
Individual BYTE WRITE controls may be tied LOW
Single R/W# (read/write) control pin
CKE# pin to enable clock and suspend operations
Three chip enables for simple depth expansion
Clock-controlled and registered addresses, data
I/Os and control signals
Internally self-timed, fully coherent WRITE
Internally self-timed, registered outputs to
eliminate the need to control OE#
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Linear or Interleaved Burst Modes
Burst feature (optional)
100-pin TQFP package
165-pin FBGA package
Pin/function compatibility with 2Mb, 4Mb, and
8Mb ZBT SRAM
OPTIONS
Timing (Access/Cycle/MHz)
3.5ns/6ns/166 MHz
4.2ns/7.5ns/133 MHz
5ns/10ns/100 MHz
Configurations
3.3V V
DD
, 3.3V or 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
2.5V V
DD
, 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
Packages
100-pin TQFP
TQFPMARKING*
-6
-7.5
-10
MT55L1MY18P
MT55L512Y32P
MT55L512Y36P
MT55V1MV18P
MT55V512V32P
MT55V512V36P
T
*A part marking guide for the FBGA devices can be found on Micron’shttp://www. micronsemi.com/support/index.html.
MT55L512Y 32PT-7.5MT55L1MY18P, MT55V1MV18P,
MT55L512Y32P, MT55V512V32P,
MT55L512Y36P, MT55V512V36P
3.3V V
DD
, 3.3V or 2.5V I/O; 2.5V V
DD
2.5V I/O
100-Pin TQFP
1
NOTE:
1. JEDEC-standard MS-026 BHA (LQFP).
165-Pin FBGA
(Preliminary Package Data)
GENERAL DESCRIPTION
The Micron
Zero Bus Turnaround
(ZBT
) SRAM
family employs high-speed, low-power CMOS designs
using an advanced CMOS process.
Micron’s 16Mb ZBT SRAMs integrate a 1 Meg x 18,
512K x 32, or 512K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. These SRAMs are optimized for 100 percent
bus utilization, eliminating any turnaround cycles for
READ to WRITE, or WRITE to READ, transitions. All
synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input (CLK).
The synchronous inputs include all addresses, all data