
1
512K x 18 2.5V V
DD
, HSTL, QDRb2 SRAM
MT54V512H18A.p65 – Rev. 3/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
512K x 18
2.5V V
DD
, HSTL, QDRb2 SRAM
9Mb QDR SRAM
2-Word Burst
FEATURES
9Mb Density (512K x 18)
Separate independent read and write data ports
with concurrent transactions
100% bus utilization DDR READ and WRITE
operation
High frequency operation with future migration to
higher clock frequencies
Fast clock to valid data times
Full data coherency, providing most current data
Two-tick burst counter for low DDR transaction
size
Double data rate operation on read and write ports
Two input clocks (K and K#) for precise DDR
timing at clock rising edges only
Two output clocks (C and C#) for precise flight
time and clock skew matching—clock and data
delivered together to receiving device
Single address bus
Simple control logic for easy depth expansion
Internally self-timed, registered writes
+2.5V core and HSTL I/O
Clock-stop capability
13x15mm, 1mm pitch, 11 x 15 grid FBGA package
User programmable impedence output
JTAG boundary scan
OPTIONS
Clock Cycle Timing
6ns (167 MHz)
7.5ns (133 MHz)
10ns (100 MHz)
MARKING
-6
-7.5
-10
Configuration
512K x 18
MT54V512H18A
Package
165-pin, 13mm x 15mm FBGA
F
165-Pin FBGA
MT54V512H18A
GENERAL DESCRIPTION
The Micron
QDR (Quad Data Rate ) Synchro-
nous Pipelined Burst SRAM employs high-speed, low-
power CMOS designs using an advanced 6T CMOS
process. The QDR architecture consists of two separate
DDR (double data rate) ports to access the memory
array. The read port has dedicated data outputs to
support READ operations. The write port has dedicated
data inputs to support WRITE operations. This architec-
ture eliminates the need for high-speed bus turnaround.
Access to each port is accomplished using a common
address bus. Addresses for reads and writes are latched
on rising edges of the K and K# input clocks, respec-
tively. Each address location is associated with two 18-
bit words that burst sequentially into or out of the
device. Since data can be transferred into
and
out of
the device on every rising edge of both clocks (K, K#, C
and C#) memory bandwidth is maximized while sim-
plifying system design by eliminating bus turnarounds.
Depth expansion is accomplished with port selects
for each port (read R#, write W#) which are received at
K rising edge. Port selects permit independent port
operation. All synchronous inputs pass through regis-
ters controlled by the K or K# input clock rising edges.
Active LOW byte writes (BW0#, BW1#) permit byte
write selection. Write data and byte writes are regis-
tered on the rising edges of both K and K#.
The addressing within each burst of two is fixed and
sequential, beginning with the lowest and ending with
VALID PART NUMBERS
PART NUMBER
MT54V512H18AF-xx
DESCRIPTION
512K x 18, QDRb2 FBGA