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| 型號(hào)： | MT47H128M8HQ-187ELAT:E |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| 封裝： | 8 X 11.50 MM, ROHS COMPLIANT, FBGA-60 |
| 文件頁(yè)數(shù)： | 56/133頁(yè) |
| 文件大小： | 9170K |
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Table 10: DDR2 IDD Specifications and Conditions (Die Revisions E, G, and H) (Continued)
Notes: 1–7 apply to the entire table
Parameter/Condition
Symbol Configuration -187E
-25E/
-25
-3E/
-3
-37E
-5E
Units
Operating burst write current:
All banks open, continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS MAX
(IDD), tRP = tRP (IDD); CKE is HIGH,
CS# is HIGH between valid com-
mands; Address bus inputs are
switching; Data bus inputs are
switching
IDD4W
x4
190
145
120
110
90
mA
x8
210
160
135
125
105
x16
405
315
200
180
160
Operating burst read current:
All banks open, continuous burst
reads, IOUT = 0mA; BL = 4, CL = CL
(IDD), AL = 0; tCK = tCK (IDD), tRAS =
tRAS MAX (IDD), tRP = tRP (IDD); CKE
is HIGH, CS# is HIGH between valid
commands; Address bus inputs are
switching; Data bus inputs are
switching
IDD4R
x4
190
145
120
110
90
mA
x8
210
160
135
125
105
x16
420
320
220
180
160
Burst refresh current: tCK = tCK
(IDD); REFRESH command at every
tRFC (IDD) interval; CKE is HIGH, CS#
is HIGH between valid commands;
Other control and address bus in-
puts are switching; Data bus inputs
are switching
IDD5
x4, x8
265
235
215
210
205
mA
x16
300
280
270
250
240
Self refresh current: CK and CK#
at 0V; CKE
≤ 0.2V; Other control
and address bus inputs are floating;
Data bus inputs are floating
IDD6
x4, x8, x16
7
mA
IDD6L
5
Operating bank interleave read
current: All bank interleaving
reads, IOUT = 0mA; BL = 4, CL = CL
(IDD), AL = tRCD (IDD) - 1 × tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD
= tRRD (IDD), tRCD = tRCD (IDD); CKE
is HIGH, CS# is HIGH between valid
commands; Address bus inputs are
stable during deselects; Data bus in-
puts are switching; See on page
for details
IDD7
x4, x8
425
335
280
270
260
mA
x16
520
440
350
330
300
Notes: 1. IDD specifications are tested after the device is properly initialized. 0°C ≤ TC ≤ +85°C.
2. VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VDDL = +1.8V ±0.1V, VREF = VDDQ/2.
3. IDD parameters are specified with ODT disabled.
1Gb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – IDD Parameters
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. S 10/09 EN
29
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT47H128M8HQ-25AT | 制造商:MICRON 制造商全稱(chēng):Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HQ-25EAT | 制造商:MICRON 制造商全稱(chēng):Micron Technology 功能描述:DDR2 SDRAM |
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