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| 型號(hào)： | MT47H128M8HQ-187ELAT:E |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| 封裝： | 8 X 11.50 MM, ROHS COMPLIANT, FBGA-60 |
| 文件頁(yè)數(shù)： | 105/133頁(yè) |
| 文件大?。?/td> | 9170K |
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READ with auto
precharge enabled/
WRITE with auto
precharge enabled:
The READ with auto precharge enabled or WRITE with auto pre-
charge enabled states can each be broken into two parts: the
access period and the precharge period. For READ with auto pre-
charge, the precharge period is defined as if the same burst was
executed with auto precharge disabled and then followed with
the earliest possible PRECHARGE command that still accesses all
of the data in the burst. For WRITE with auto precharge, the pre-
charge period begins when tWR ends, with tWR measured as if
auto precharge was disabled. The access period starts with regis-
tration of the command and ends where the precharge period
(or tRP) begins. This device supports concurrent auto precharge
such that when a READ with auto precharge is enabled or a
WRITE with auto precharge is enabled, any command to other
banks is allowed, as long as that command does not interrupt
the read or write data transfer already in process. In either case,
all other related limitations apply (contention between read da-
ta and write data must be avoided).
The minimum delay from a READ or WRITE command with auto precharge enabled to
a command to a different bank is summarized in Table 39 (page 73).
4. REFRESH and LOAD MODE commands may only be issued when all banks are idle.
5. Not used.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
8. A WRITE command may be applied after the completion of the READ burst.
9. Requires appropriate DM.
10. The number of clock cycles required to meet tWTR is either two or tWTR/tCK, whichever
is greater.
Table 39: Minimum Delay with Auto Precharge Enabled
From Command (Bank n)
To Command (Bank m)
Minimum Delay
(with Concurrent Auto Precharge)
Units
WRITE with auto precharge
READ or READ with auto precharge
(CL - 1) + (BL/2) + tWTR
tCK
WRITE or WRITE with auto precharge
(BL/2)
tCK
PRECHARGE or ACTIVATE
1
tCK
READ with auto precharge
READ or READ with auto precharge
(BL/2)
tCK
WRITE or WRITE with auto precharge
(BL/2) + 2
tCK
PRECHARGE or ACTIVATE
1
tCK
DESELECT
The DESELECT function (CS# HIGH) prevents new commands from being executed by
the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in
progress are not affected. DESELECT is also referred to as COMMAND INHIBIT.
1Gb: x4, x8, x16 DDR2 SDRAM
Commands
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. S 10/09 EN
73
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT47H128M8HQ-25AT | 制造商:MICRON 制造商全稱(chēng):Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HQ-25EAT | 制造商:MICRON 制造商全稱(chēng):Micron Technology 功能描述:DDR2 SDRAM |
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