參數(shù)資料
型號(hào): MT47H128M8HQ-187ELAT:E
元件分類: DRAM
英文描述: 128M X 8 DDR DRAM, 0.35 ns, PBGA60
封裝: 8 X 11.50 MM, ROHS COMPLIANT, FBGA-60
文件頁(yè)數(shù): 17/133頁(yè)
文件大小: 9170K
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)當(dāng)前第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)
Figure 66: Data Input Timing
DQS
DQS#
tDQSH tWPST
tDQSL
tDSS 2 tDSH 1
tDSH 1
tDSS 2
DM
DQ
CK
CK#
T1
T0
T1n
T2
T2n
T3
T4
T3n
DI
Don’t Care
Transitioning Data
tWPRE
3
WL - tDQSS (NOM)
Notes: 1. tDSH (MIN) generally occurs during tDQSS (MIN).
2. tDSS (MIN) generally occurs during tDQSS (MAX).
3. Subsequent rising DQS signals must align to the clock within tDQSS.
4. WRITE command issued at T0.
5. For x16, LDQS controls the lower byte and UDQS controls the upper byte.
6. WRITE command with WL = 2 (CL = 3, AL = 0) issued at T0.
PRECHARGE
Precharge can be initiated by either a manual PRECHARGE command or by an autopre-
charge in conjunction with either a READ or WRITE command. Precharge will deacti-
vate the open row in a particular bank or the open row in all banks. The PRECHARGE
operation is shown in the previous READ and WRITE operation sections.
During a manual PRECHARGE command, the A10 input determines whether one or all
banks are to be precharged. In the case where only one bank is to be precharged, bank
address inputs determine the bank to be precharged. When all banks are to be pre-
charged, the bank address inputs are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state and must be activated prior to
any READ or WRITE commands being issued to that bank. When a single-bank PRE-
CHARGE command is issued, tRP timing applies. When the PRECHARGE (ALL) com-
mand is issued, tRPA timing applies, regardless of the number of banks opened.
1Gb: x4, x8, x16 DDR2 SDRAM
PRECHARGE
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. S 10/09 EN
113
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
相關(guān)PDF資料
PDF描述
MT48LC2M32B1TG-7 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86
MT48LC32M4A2P-7ELIT:G 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
MT55L256L18FT-12TR 256K X 18 ZBT SRAM, 9 ns, PQFP100
MT55L256L32FT-12 256K X 32 ZBT SRAM, 9 ns, PQFP100
MT55L512V18PF-6 512K X 18 ZBT SRAM, 3.5 ns, PBGA165
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT47H128M8HQ-25AT 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
MT47H128M8HQ-25EAT 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM