參數(shù)資料
型號(hào): MT47H128M8HQ-187ELAT:E
元件分類: DRAM
英文描述: 128M X 8 DDR DRAM, 0.35 ns, PBGA60
封裝: 8 X 11.50 MM, ROHS COMPLIANT, FBGA-60
文件頁(yè)數(shù): 55/133頁(yè)
文件大小: 9170K
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)當(dāng)前第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)
Table 10: DDR2 IDD Specifications and Conditions (Die Revisions E, G, and H)
Notes: 1–7 apply to the entire table
Parameter/Condition
Symbol Configuration -187E
-25E/
-25
-3E/
-3
-37E
-5E
Units
Operating one bank active-
precharge current:
tCK = tCK (IDD), tRC = tRC (IDD), tRAS
= tRAS MIN (IDD); CKE is HIGH, CS# is
HIGH between valid commands; Ad-
dress bus inputs are switching; Data
bus inputs are switching
IDD0
x4, x8
115
90
85
70
mA
x16
180
150
135
110
Operating one bank active-read-
precharge current: IOUT = 0mA; BL
= 4, CL = CL (IDD), AL = 0; tCK = tCK
(IDD), tRC = tRC (IDD), tRAS = tRAS
MIN (IDD), tRCD = tRCD (IDD); CKE is
HIGH, CS# is HIGH between valid
commands; Address bus inputs are
switching; Data pattern is same as
IDD4W
IDD1
x4, x8
130
110
100
95
90
mA
x16
210
175
130
120
115
Precharge power-down current:
All banks idle; tCK = tCK (IDD); CKE
is LOW; Other control and address
bus inputs are stable; Data bus in-
puts are floating
IDD2P
x4, x8, x16
7
mA
Precharge quiet standby
current: All banks idle;
tCK = tCK (IDD); CKE is HIGH, CS# is
HIGH; Other control and address
bus inputs are stable; Data bus in-
puts are floating
IDD2Q
x4, x8
60
50
40
35
mA
x16
90
75
65
45
40
Precharge standby current: All
banks idle; tCK = tCK (IDD); CKE is
HIGH, CS# is HIGH; Other control
and address bus inputs are switch-
ing; Data bus inputs are switching
IDD2N
x4, x8
60
50
40
35
mA
x16
95
80
70
50
40
Active power-down current: All
banks open; tCK = tCK (IDD); CKE is
LOW; Other control and address
bus inputs are stable; Data bus in-
puts are floating
IDD3Pf
Fast exit
MR12 = 0
50
40
30
mA
IDD3Ps
Slow exit
MR12 = 1
10
Active standby current: All banks
open; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is
HIGH, CS# is HIGH between valid
commands; Other control and ad-
dress bus inputs are switching; Data
bus inputs are switching
IDD3N
x4, x8
70
60
55
45
40
mA
x16
95
85
75
60
55
1Gb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – IDD Parameters
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. S 10/09 EN
28
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
相關(guān)PDF資料
PDF描述
MT48LC2M32B1TG-7 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86
MT48LC32M4A2P-7ELIT:G 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
MT55L256L18FT-12TR 256K X 18 ZBT SRAM, 9 ns, PQFP100
MT55L256L32FT-12 256K X 32 ZBT SRAM, 9 ns, PQFP100
MT55L512V18PF-6 512K X 18 ZBT SRAM, 3.5 ns, PBGA165
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT47H128M8HQ-25AT 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
MT47H128M8HQ-25EAT 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM