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參數(shù)資料
| 型號(hào)： | MT47H128M8HQ-187ELAT:E |
| 元件分類： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| 封裝： | 8 X 11.50 MM, ROHS COMPLIANT, FBGA-60 |
| 文件頁數(shù)： | 23/133頁 |
| 文件大?。?/td> | 9170K |
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Table 43: Truth Table – CKE
Notes 1–4 apply to the entire table
Current State
CKE
Command (n)
CS#, RAS#, CAS#,
WE#
Action (n)
Notes
Previous Cycle
(n - 1)
Current
Cycle (n)
Power-down
L
X
Maintain power-down
L
H
DESELECT or NOP
Power-down exit
Self refresh
L
X
Maintain self refresh
L
H
DESELECT or NOP
Self refresh exit
Bank(s) active
H
L
DESELECT or NOP Active power-down entry
All banks idle
H
L
DESELECT or NOP
Precharge power-down
entry
H
L
Refresh
Self refresh entry
H
Shown in Table 36 (page 69)
Notes: 1. CKE (n) is the logic state of CKE at clock edge n; CKE (n - 1) was the state of CKE at the
previous clock edge.
2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge n.
3. Command (n) is the command registered at clock edge n, and action (n) is a result of
command (n).
4. The state of ODT does not affect the states described in this table. The ODT function is
not available during self refresh (see ODT Timing (page 127) for more details and specif-
ic restrictions).
5. Power-down modes do not perform any REFRESH operations. The duration of power-
down mode is therefore limited by the refresh requirements.
6.
“X” means “Don’t Care” (including floating around VREF) in self refresh and power-
down. However, ODT must be driven high or low in power-down if the ODT function is
enabled via EMR.
7. All states and sequences not shown are illegal or reserved unless explicitly described else-
where in this document.
8. Valid commands for power-down entry and exit are NOP and DESELECT only.
9. On self refresh exit, DESELECT or NOP commands must be issued on every clock edge
occurring during the tXSNR period. READ commands may be issued only after tXSRD
(200 clocks) is satisfied.
10. Valid commands for self refresh exit are NOP and DESELECT only.
11. Power-down and self refresh can not be entered while READ or WRITE operations,
LOAD MODE operations, or PRECHARGE operations are in progress. See SELF REFRESH
(page 115) and SELF REFRESH (page 75) for a list of detailed restrictions.
12. Minimum CKE high time is tCKE = 3 × tCK. Minimum CKE LOW time is tCKE = 3 × tCK.
This requires a minimum of 3 clock cycles of registration.
13. Self refresh mode can only be entered from the all banks idle state.
14. Must be a legal command, as defined in Table 36 (page 69).
1Gb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. S 10/09 EN
119
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT47H128M8HQ-25AT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HQ-25EAT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
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