參數(shù)資料
型號(hào)： MT47H128M8HQ-187ELAT:E
元件分類： DRAM
英文描述： 128M X 8 DDR DRAM, 0.35 ns, PBGA60
封裝： 8 X 11.50 MM, ROHS COMPLIANT, FBGA-60
文件頁數(shù)： 111/133頁
文件大小： 9170K
CAS Latency (CL)
The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 35 (page 76). CL is
the delay, in clock cycles, between the registration of a READ command and the availa-
bility of the first bit of output data. The CL can be set to 3, 4, 5, 6, or 7 clocks, depending
on the speed grade option being used.
DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be
used as an unknown operation otherwise incompatibility with future versions may result.
DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This fea-
ture allows the READ command to be issued prior to tRCD (MIN) by delaying the
internal command to the DDR2 SDRAM by AL clocks. The AL feature is described in
Examples of CL = 3 and CL = 4 are shown in Figure 36; both assume AL = 0. If a READ
command is registered at clock edge n, and the CL is m clocks, the data will be available
nominally coincident with clock edge n + m (this assumes AL = 0).
Figure 36: CL
DO
n + 3
DO
n + 2
DO
n + 1
CK
CK#
Command
DQ
DQS, DQS#
CL = 3 (AL = 0)
READ
T0
T1
T2
Don’t care
Transitioning data
NOP
DO
n
T3
T4
T5
NOP
T6
NOP
DO
n + 3
DO
n + 2
DO
n + 1
CK
CK#
Command
DQ
DQS, DQS#
CL = 4 (AL = 0)
READ
T0
T1
T2
NOP
DO
n
T3
T4
T5
NOP
T6
NOP
Notes: 1. BL = 4.
2. Posted CAS# additive latency (AL) = 0.
3. Shown with nominal tAC, tDQSCK, and tDQSQ.
1Gb: x4, x8, x16 DDR2 SDRAM
Mode Register (MR)
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. S 10/09 EN
79
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT47H128M8HQ-25AT 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
MT47H128M8HQ-25EAT 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
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