
MPC509
USER’S MANUAL
SYSTEM INTERFACE UNIT
Rev. 15 June 98
MOTOROLA
5-5
Table 5-2 SIUMCR Bit Settings
Bit(s)
Name
Description
0
SIUFRZ
SIU freeze
0 = Decrementer and time base registers and the periodic interrupt timer continue to run while
internal freeze signal is asserted (reset value).
1 = Decrementer and time base registers and the periodic interrupt timer stop while the internal
freeze signal is asserted.
Refer to
5.3.3 Internal Module Select Logic
and
SECTION 8 DEVELOPMENT SUPPORT
for
information on the freeze signal.
Reserved
Checkstop reset enable
0 = No action taken when SIU receives the checkstop signal from the CPU and debug mode not
enabled (reset value).
1 = SIU causes a reset upon receiving checkstop signal from CPU and debug mode not enabled.
If debug mode is enabled, the MCU enters debug mode when the checkstop signal is received,
regardless of CSR value. Refer to the RCPU Reference Manual(RCPURM/AD) for more infor-
mation on checkstop resets.
Burst style: BDIP or LAST
0 = BDIP pin uses BDIP timing (reset value): assert BDIP during burst, negate BDIP during last
beat of burst
1 = BDIP pin uses LAST timing: assert LAST during last beat of burst
Refer to
5.5.16.6 Synchronous Burst Interface
for more information.
Reserved
Supervisor/unrestricted space. These bits control access to certain SIU registers. (Other regis-
ters are always supervisor access only.) The access restrictions for each register are shown in
Table 5-1
.
00 = Unrestricted access (reset value)
01 = Supervisor mode access only
10 = Supervisor mode write access only, unrestricted read access
11 = Supervisor mode access only
Debug register lock. This bit can be written only when internal freeze signal is asserted. DLK
allows development software to configure show cycles and prevent normal software from subse-
quently changing this configuration. This bit overrides the LOK in controlling the LSHOW field.
0 = LSHOW field in SIUMCR can be written to (reset value).
1 = Writes to LSHOW field are not allowed.
Register lock. Once this bit is set, writes to the SIUMCR and chip-select registers have no effect
and cause a data error to be generated in the internal bus. In normal operation, this is a set-only
bit; once set, it cannot be cleared by software. When the internal freeze signal is asserted, the
bit can be set or cleared by software.
0 = Normal operation (reset value)
1 = All bits in the SIUMCR and all of the chip-select registers are locked
Reserved
L-bus show cycles
00 = Disable show cycles for all internal L-bus cycles (reset value)
01 = Show address and data of all internal L-bus write cycles
10 = Reserved
11 = Show address and data of all internal L-bus cycles
Refer to
5.4.13 Show Cycles
for more information.
Part number. This read-only field is mask programmed with a code corresponding to the number
of the MCU.
Mask number. This read-only field is mask programmed with a code corresponding to the mask
number of the MCU.
1:2
—
3
CSR
4
LST
5
—
6:7
SUP
8
DLK
9
LOK
10:13
—
14:15
LSHOW
16:23
PARTNUM
24:31
MASKNUM