
MOTOROLA
8-2
DEVELOPMENT SUPPORT
Rev. 15 June 98
MPC509
USER’S MANUAL
serialized, and all internal fetch cycles appear on the external bus. Processor perfor-
mance is therefore much lower than when working in regular mode.
The mechanism described below allows tracking of the program instructions flow with
almost no performance degradation. The information provided externally may be cap-
tured and compressed and then parsed by a post-processing program using the
microarchitecture defined below.
The RCPU implements a prefetch queue combined with parallel, out of order, pipe-
lined execution. Instructions progress inside the processor from fetch to retire. An
instruction retires from the machine only after it, and all preceding instructions, finish
execution with no exception. Therefore only retired instructions can be considered
architecturally executed.
These features, together with the fact that most fetch cycles are performed internally
(e.g. from the I-cache), increase performance but make it very difficult to provide the
user with the real program trace.
In order to reconstruct a program trace, the program code and the following additional
information from the MCU are needed:
A description of the last fetched instruction (stall, sequential, branch not taken,
branch direct taken, branch indirect taken, exception taken).
The addresses of the targets of all indirect flow change. Indirect flow changes in-
clude all branches using the link and count registers as the target address, all ex-
ceptions, and
rfi
and
mtmsr
because they may cause a context switch.
The number of instructions canceled each clock.
Reporting on program trace during retirement would significantly complicate the visi-
bility support and increase the die size. (Complications arise because more than one
instruction can retire in a clock cycle, and because it is harder to report on indirect
branches during retirement.) Therefore, program trace is reported during fetch. Since
not all fetched instructions eventually retire, an indication on canceled instructions is
reported.
Instructions are fetched sequentially until branches (direct or indirect) or exceptions
appear in the program flow or some stall in execution causes the machine not to fetch
the next address. Instructions may be architecturally executed, or they may be can-
celed in some stage of the machine pipeline.
The following sections define how this information is generated and how it should be
used to reconstruct the program trace. The issue of data compression that could
reduce the amount of memory needed by the debug system is also mentioned.
8.1.1 Indirect Change-of-Flow Cycles
An indirect change-of-flowattribute is attached to all fetch cycles that result from indi-
rect flow changes. Indirect flow changes include the following types of instructions or
events:
Assertion or negation of VSYNC.