
MPC509
USER’S MANUAL
SYSTEM INTERFACE UNIT
Rev. 15 June 98
MOTOROLA
5-31
The I-bus show cycles are always address-only cycles. They do not wait for the inter-
nal transaction to complete. L-bus show cycles have both address and data and
appear on the external bus after the internal cycle is completed.
Aborted L-bus cycles do not result in a show cycle. (The load/store unit of the proces-
sor may abort the cycle when the previous cycle terminates with a transfer error, or
when an exception occurs during the current cycle.)
Aborted I-bus cycles do result in a show cycle. (The processor may abort an I-bus
cycle when it encounters a branch; it aborts the fetch just starting on a wrong path. In
addition, the processor aborts the cycle on a cache hit.)
Note that I-bus show cycles are not burst.
A show cycle involves transfer start (TS), address (ADDR), cycle type (CT), address
type (AT), burst (BURST) and read/write (WR) pins. The data phase of an L-bus show
cycle looks like a write cycle going out on the external bus. The address and data
phases of a show cycle last one clock cycle each. No termination is needed for either
phase, as all show cycles are automatically terminated inside the SIU. For the L-bus
show cycles (I-bus show cycles are address only), the data phase always follows the
address phase by one clock cycle. The L-bus show cycle does not start until the inter-
nal cycle completes. This allows all show cycles to complete in two clock cycles.
Show cycles require several holding registers in the SIU to hold address and data of
an L-bus cycle and address of an I-bus cycle until the E-bus is available and the show
cycle is run. When these holding registers are full, the internal bus (or buses) are held
up by the SIU while it waits for the show cycle to complete.
During cross-bus accesses, the show cycle is associated with the bus initiating the
transaction. For example, if I-bus show cycles are enabled and L-bus show cycles are
disabled, then an instruction fetch from L-RAM will show up as an address-only I-bus
show cycle, and an L-bus access to I-memory would not have a show cycle.
Refer to
SECTION 8 DEVELOPMENT SUPPORT
for more information on show
cycles.
5.4.14 Storage Reservation Support
The PowerPC
lwarx
(load word and reserve indexed) and
stwcx.
(store word condi-
tional indexed) instructions in combination permit the atomic update of a storage
location. Refer to the RCPU Reference Manual(RCPURM/AD) for details on these
instructions.
The storage reservation protocol supports a multi-level bus structure like the one
shown in
Figure 5-10
. In this figure, the E-bus is a PowerPC bus interfaced to a non-
local bus, such as a PC/AT or VME bus, through a non-local bus interface. For each
local bus, storage reservation is handled by the local reservation logic.
The protocol tries to optimize reservation cancellation such that a PowerPC processor
is notified of the loss of a storage reservation on a remote bus only when it has issued