參數(shù)資料
型號(hào): MPC509
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: Highly Integrated, Low-Power, 32-Bit Microcontroller
中文描述: 32-BIT, RISC MICROCONTROLLER, PQFP16
文件頁(yè)數(shù): 92/300頁(yè)
文件大?。?/td> 3744K
代理商: MPC509
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MOTOROLA
4-6
INSTRUCTION CACHE
Rev. 15 June 98
MPC509
USER’S MANUAL
The transfer begins with the word requested by the instruction unit (critical word first),
followed by any remaining words of the line, then by any remaining words at the begin-
ning of the line (wrap around). As the missed instruction is received from the bus, it is
immediately delivered to the instruction unit and also written to the burst buffer.
As subsequent instructions are received from the bus they are also written into the
burst buffer and, if needed, delivered to the instruction unit (stream hit) either directly
from the bus or from the burst buffer. When the entire line resides in the burst buffer,
it is written to the cache array if the cache array is not busy with an instruction unit
request.
If a bus error is encountered on the access to the requested instruction, a machine
check interrupt is taken. If a bus error occurs on any access to other words in the line,
the burst buffer is marked invalid and the line is not written to the array. If no bus error
is encountered, the burst buffer is marked valid and eventually is written to the array.
Together with the missed word, an indication may arrive from the I-bus that the mem-
ory device is non-cacheable. If such an indication is received, the line is not written to
the cache, so that subsequent references to the same line will cause the line to be
refetched.
4.5 Cache Commands
The MPC509 instruction cache supports the PowerPC invalidate instruction together
with some additional commands that help control the cache and debug the information
stored in it. The additional commands are implemented using the three special pur-
pose control registers ICCST, ICADR, and ICDAT.
Most of the commands are executed immediately after the control register is written
and cannot generate any errors. When these commands are executed, there is no
need to check the error status in the ICCST.
Some commands may take longer and may generate errors. In the MPC509, only
load
& lock
is such a command. When executing this command, the user needs to insert
an
isync
instruction immediately after the I-cache command and check the error sta-
tus in the ICCST after the
isync
. The error type bits in the ICCST are sticky, allowing
the user to perform a series of I-cache commands before checking the termination sta-
tus. These bits are set by hardware and cleared by software.
All cache commands except the
icbi
CPU instruction require setting the appropriate
bits in the ICCST. Since the ICCST is a supervisor-level register, only the
icbi
instruc-
tion can be performed at the user privilege level.
4.5.1 Instruction Cache Block Invalidate
The MPC509 implements the PowerPC instruction cache block invalidate (
icbi
) as if it
pertains only to the MPC509 instruction cache. This instruction does not broadcast on
the external bus and the CPU does not snoop this instruction if broadcast by other
masters.
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