參數(shù)資料
型號(hào): MPC509
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: Highly Integrated, Low-Power, 32-Bit Microcontroller
中文描述: 32-BIT, RISC MICROCONTROLLER, PQFP16
文件頁(yè)數(shù): 241/300頁(yè)
文件大?。?/td> 3744K
代理商: MPC509
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MPC509
USER’S MANUAL
DEVELOPMENT SUPPORT
Rev. 15 June 98
MOTOROLA
8-23
8.3.1.1 Development Serial Clock
In clocked mode (see
8.3.3 Development Port Clock Mode Selection
), the develop-
ment serial clock (DSCK) is used to shift data into and out of the development port shift
register. The DSCK and DSDI inputs are synchronized to the on-chip system clock,
thereby minimizing the chance of propagating metastable states into the serial state
machine. The values of the pins are sampled during the low phase of the system clock.
At the rising edge of the system clock, the sampled values are latched internally. One
quarter clock later, the latched values are made available to the development support
logic.
In clocked mode, detection of the rising edge of the synchronized clock causes the
synchronized data from the DSDI pin to be loaded into the least significant bit of the
shift register. This transfer occurs one quarter clock after the next rising edge of the
system clock. At the same time, the new most significant bit of the shift register is pre-
sented at the PLLL/DSDO pin. Future references to the DSCK signal imply the internal
synchronized value of the clock. The DSCK input must be driven either high or low at
all times and not allowed to float. A typical target environment would pull this input low
with a resistor.
To allow the synchronizers to operate correctly, the development serial clock fre-
quency must not exceed one half of the system clock frequency. The clock may be
implemented as a free-running clock. The shifting of data is controlled by ready and
start signals so the clock does not need to be gated with the serial transmissions.
Refer to
8.3.5 Trap-Enable Input Transmissions
and
8.3.6 CPU Input Transmissions
.
The DSCK pin is also used during reset to enable debug mode and immediately fol-
lowing reset to optionally cause immediate entry into debug mode following reset. This
is described in section
8.4.1 Enabling Debug Mode
and
8.4.2 Entering Debug Mode
.
8.3.1.2 Development Serial Data In
Data to be transferred into the development port shift register is presented at the
development serial data in (DSDI) pin by external logic. To be sure that the correct
value is used internally, transitions on the DSDI pin should occur at least a setup time
ahead of the rising edge of the DSCK signal (if in clocked mode) or a setup time ahead
of the rising edge of the system clock, whichever is greater. This will allow operation
of the development port either asynchronously or synchronously with the system
clock. The DSDI input must be driven either high or low at all times and not allowed to
float. A typical target environment would pull this input low with a resistor.
When the processor is not in debug mode (freeze not indicated on VFLS[0:1] pins) the
data received on the DSDI pin is transferred to the trap enable control register. When
the processor is in debug mode, the data received on the DSDI pin is provided to the
debug mode interface. Refer to
8.3.5 Trap-Enable Input Transmissions
and
8.3.6 CPU
Input Transmissions
for additional information.
The DSDI pin is also used at reset to control overall chip reset configuration and imme-
diately following reset to determine the development port clock mode. See
8.3.3
Development Port Clock Mode Selection
for more information.
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