
MPC509
USER’S MANUAL
DEVELOPMENT SUPPORT
Rev. 15 June 98
MOTOROLA
8-7
8.1.3.4 Cycle Type, Write/Read, and Address Type Pins
Cycle type pins (CT[0:3]) indicate the type of bus cycle being performed. During show
cycles, these pins are used to determine the internal address being accessed.
Table
8-6
summarizes cycle type encodings.
Notice in
Table 8-6
that during an instruction fetch (AT1 = 1) to internal memory or to
external memory resulting in a cache hit, a logic level of zero on the WR pin indicates
that the cycle is the result of an indirect change-of-flow. The indirect change-of-flow
attribute is also indicated by a cycle type encoding of 0001 when AT1 = 1. Refer to
8.1.1.1 Marking the Indirect Change-of-Flow Attribute
for additional information.
8.1.4 External Hardware During Program Trace
When program trace is needed, external hardware needs to record the status pins
(VF[0:2] and VFLS[0:1]) of each clock and record the address of all cycles marked with
the indirect change-of-flow attribute.
Table 8-6 Cycle Type Encodings
CT[0:3]
0000
Description
Normal external bus cycle
If address type is data (AT1 = 0), this is a data access to the external bus
and the start of a reservation.
If address type is instruction (AT1 = 1), this cycle type indicates that an
external address is the destination of an indirect change-of-flow.
External bus cycle to emulation memory replacing internal I-bus or L-bus
memory. An instruction access (AT1 = 1) with an address that is the target
of an indirect change-of-flow is indicated as a logic level zero on the WR
output.
Normal external bus cycle access to a port replacement chip used for
emulation support.
Access to internal I-bus memory. An instruction access (AT1 = 1) with an
address that is the target of an indirect change-of-flow is indicated as a logic
level zero on the WR output.
Access to internal L-bus memory. An instruction access (AT1 = 1) with an
address that is the target of an indirect change-of-flow is indicated as a logic
level zero on the WR output.
Cache hit on external memory address not controlled by chip selects. An
instruction access (AT1 = 1) with an address that is the target of an indirect
change-of-flow is indicated as a logic level zero on the WR output.
Access to an internal register.
Cache hit on external memory address controlled by CSBOOT.
Cache hit on external memory address controlled by CS1.
Cache hit on external memory address controlled by CS2.
Cache hit on external memory address controlled by CS3.
Cache hit on external memory address controlled by CS4.
Cache hit on external memory address controlled by CS5.
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
An instruction access (AT1 = 1) with an address that is the target of an
indirect change-of-flow is indicated as a logic level zero on the WR output.
Reserved
1110
1111