
MPC509
USER’S MANUAL
SYSTEM INTERFACE UNIT
Rev. 15 June 98
MOTOROLA
5-53
BDIP and LAST are the early termination control signals for burst cycles. A memory
device with a type 1 burst interface may have a BDIP signal as one of its inputs. A
memory device with a type 2 burst interface has a LAST signal as one of its inputs.
Refer to
5.5.16.6 Synchronous Burst Interface
for a description of these interface
types.
A device may or may not have the ability to hold off its data output until the data bus
is available to the device. To be able to hold off its data the device needs an OE control
input, and if the device is burstable it also needs the ability to suspend its internal state
machine from advancing to the next data beat until the data bus has been granted to
it. An example of this is a memory device with burst address advance control such as
BDIP to control the incrementing of its internal address counter.
5.5.13.1 Interface Type Descriptions
Table 5-27
lists the characteristics of each interface type. Note that if software pro-
grams the ITYPE field to one of the reserved values, the chip-select signal will never
be asserted.
Table 5-27 Interface Types
ITYPE
(Binary)
Interface Type
0000
Generic asynchronous region with output buffer turn-off time of less than or equal
to one clock period (see
5.5.13.2 Turn-Off Times for Different Interface
Types
). A device of this type cannot be pipelined. Refer to
Figure 5-17
and
Fig-
ure 5-18
.
Generic asynchronous region with output buffer turn-off time of two clock periods
(see
5.5.13.2 Turn-Off Times for Different Interface Types
). A device of this
type cannot be pipelined. The chip-select logic inserts a dead clock between two
subsequent accesses to the same region of this type in order to satisfy the high
time required by the CE and WE of some memory types.
Synchronous region (no burst) with asynchronous OE. Refer to
Figure 5-19
and
Figure 5-20
. A device with this type of interface is pipelineable, can function as
an asynchronous device, and has the ability to hold off its internal data on a read
access until OE is asserted.
Note that with this interface type, if the MCU receives TA before asserting OE, OE
may still be asserted and may remain asserted.
Synchronous region (no burst) with synchronous OE. Refer to
Figure 5-21
. A de-
vice with this type of interface is pipelineable, can function as an asynchronous
device, and has the ability to hold off its internal data on a read access until OE
is asserted. The chip-select logic asserts OE for one clock cycle on accesses to
devices with this interface type.
A device with synchronous OE must be programmed for one or more wait states.
If the region is programmed for zero wait states with synchronous OE, the chip-
select logic still generates the OE as if the region were programmed for one wait
state.
Reserved.
0001
0010
0011
0100