
MPC509
USER’S MANUAL
DEVELOPMENT SUPPORT
Rev. 15 June 98
MOTOROLA
8-33
to be received on the same transmission, there is no conflict between a valid data sta-
tus and the sequencing error status.
8.3.8.2 Sequencing Error Output
The sequencing errorencoding indicates that the inputs from the external develop-
ment tool are not what the development port or the CPU was expecting. Two cases
could cause this error: 1) the processor was trying to read instructions and data was
shifted into the development port, or 2) the processor was trying to read data and an
instruction was shifted into the development port.
When a sequencing error occurs, the port terminates the CPU read or fetch cycle with
a bus error. This bus error causes the CPU to signal the development port that an
exception occurred. Since a status of sequencing error has a higher priority than a sta-
tus of exception, the port reports the sequencing error. The development port ignores
the data being shifted in while the sequencing error is shifting out. The next transmis-
sion to the port should be a new instruction or trap enable data.
Table 8-16
illustrates a typical sequence of events when a sequencing error occurs.
This example begins with CPU data being shifted into the shift register (control bit = 1)
when the processor is expecting an instruction. During the next transmission, a
sequencing error is shifted out of the development port, and the data shifted into the
shift register is thrown away. During the third transmission, the “CPU exception” status
is output, and again the data shifted into the shift register is thrown away. During the
fourth transmission, an instruction is again shifted into the development port and
fetched by the CPU for execution. Notice in this example that the development port
throws away the first two input transmissions following the one causing the sequencing
error.
8.3.8.3 CPU Exception Output
The CPU exceptionencoding is used to indicate that the CPU encountered an excep-
tion during the execution of the previous instruction in debug mode. Exceptions may
occur as the result of instruction execution (such as unimplemented opcode or arith-
metic error), because of a memory access fault, or from an external interrupt. The
exception is recognized only if the associated bit in the DER is set. When an exception
occurs, the development port ignores the data being shifted in while the CPU excep-
Table 8-16 Sequencing Error Activity
Trans #
Input to
Development Port
CPU data
(Control bit = 1)
Output from
Development Port
Depends on
previous
transmissions
Sequencing error
Port Action
CPU Action
1
Cause bus error, set
sequence error latch
Fetch instruction, take
exception because of bus
error
Signal exception to port,
begin new fetch from port
Continue to wait for
instruction from port
Fetch instruction from port
2
X (Thrown away)
Set exception latch, clear
sequencing error latch
Clear exception latch
3
X (Thrown away)
CPU exception
4
CPU instruction
Null
Send instruction to CPU at
end of transmission