參數(shù)資料
型號(hào)： MII-300GP
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 300 MHz, MICROPROCESSOR, PGA296
封裝： SPGA, 296 PIN
文件頁(yè)數(shù)： 41/257頁(yè)
文件大?。?/td> 1234K
代理商： MII-300GP
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PRELIMINARY
3-13
3
Signal Descriptions
3.2.8
Bus Cycle Control
The bus cycle control signals (ADS#, ADSC#,
BRDY#, BRDYC#, NA#, and SMIACT#)
indicate the beginning of a bus cycle and allow
system hardware to control bus cycle termina-
tion timing and address pipelining.
Address Strobe (ADS#) is an active low
output which indicates that the CPU has
driven a valid address and bus cycle definition
on the appropriate output pins. ADS# floats
during bus hold states.
Cache Address Strobe (ADSC#) performs
the same function as ADS#. ADSC# is used to
interface directly to a secondary cache
controller.
Burst Ready (BRDY#) is an active low input
that is driven by the system to indicate that the
current transfer within a burst cycle or the
current single transfer bus cycle can be termi-
nated. The CPU samples BRDY# in the second
and subsequent clocks of a cycle. BRDY# is
active during address hold states.
Cache Burst Ready (BRDYC#) performs the
same function as BRDY# and is logically ORed
with BRDY internally by the CPU. BRDYC# is
used to interface directly to a secondary cache
controller.
Next Address (NA#) is an active low input
that is driven by the system to request the next
pending bus cycle address and cycle definition
information even though all data transfers for
the current bus cycle are not complete. This
new bus cycle is referred to as a “pipelined”
cycle. If either the current or next bus cycle is a
locked cycle, a line replacement, a write-back
cycle or there is no pending bus cycle, the M II
CPU does not start a pipelined bus cycle
regardless of the state of the NA# input.
System Management Mode Active
(SMIACT#) behaves in one of two ways
depending on which SMM mode is in effect.
In SL-Compatible Mode, SMIACT# is an active
low output which indicates that the CPU is
operating in System Management Mode.
SMIACT# is asserted in response to the asser-
tion of SMI# or due to execution of SMINT
instruction. SMIACT# is also asserted during
accesses to define SMM memory if SMAC bit
CCR1 is set. The SMAC bit allows access to
SMM memory while not in SMM mode and
typically used for initialization purposes.
While in SL-compatible mode, when servicing
an SMI# interrupt or SMINT instruction,
SMIACT# remains asserted until a RSM
instruction is executed. The RSM instruction
causes the M II CPUT to exit SMM mode and
negate the SMIACT# output. If a cache inquiry
cycle occurs while SMIACT# is active, any
resulting write-back cycle is issued with
SMIACT# asserted. This occurs even thought
the write-back cycle is intended for normal
memory rather than SMM memory.
In Cyrix Enhanced Mode, SMIACT# does not
indicate that the CPU is operating in system
management mode. In Cyrix Enhanced Mode,
SMIACT# is asserted for every SMM memory
bus cycle and negated for every non-SMM
memory cycle. In this mode SMIACT# follows
the timing of MIO# and W/R#.
During RESET, the USE_SMI bit in CCR1 is
cleared. While USE_SMI is zero, SMIACT# is
always negated. SMIACT# does not float
during bus hold states, except during Cyrix
Enhanced SMM Operations.
相關(guān)PDF資料
PDF描述
MJ10000 20 A, 350 V, NPN, Si, POWER TRANSISTOR, TO-204AA
MJ1000 10 A, 60 V, NPN, Si, POWER TRANSISTOR, TO-204AA
MJ1001 10 A, 80 V, NPN, Si, POWER TRANSISTOR, TO-204AA
MJ10022 40 A, 350 V, NPN, Si, POWER TRANSISTOR, TO-204AE
MJ3000 10 A, 60 V, NPN, Si, POWER TRANSISTOR, TO-204AA
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