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| 型號(hào)： | MII-300GP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, MICROPROCESSOR, PGA296 |
| 封裝： | SPGA, 296 PIN |
| 文件頁(yè)數(shù)： | 38/257頁(yè) |
| 文件大?。?/td> | 1234K |
| 代理商： | MII-300GP |
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3-10
PRELIMINARY
Signal Descriptions
Advanci ng the S tandar ds
3.2.4
Address Parity
Address Parity (AP) is a bi-directional signal
which provides the parity associated with
address lines A31-A5. (A4 and A3 are not
included in the parity determination.) During
M II CPU generated bus cycles, while the
address bus lines are driven, AP becomes an
output supplying even address parity. During
cache inquiry cycles, AP becomes an input and
is sampled by EADS#. During cache inquiry
cycles, even-parity must be placed on the AP
line to guarantee an accurate result on the
APCHK# (Address Parity Check Status) pin.
Address Parity Check Status (APCHK#) is
driven active by the CPU when an address bus
parity error has been detected for a cache
inquiry cycle. APCHK# is asserted two clocks
after EADS# is sampled asserted, and remains
valid for one clock only. Address parity errors
signaled by APCHK# have no effect on
processor execution.
3.2.5
Data Bus
Data Bus (D63-D0) lines carry three-state,
bi-directional signals between the M II CPU and
the system (i.e., external memory and I/O
devices). The data bus transfers data to the M II
CPU during memory read, I/O read, and inter-
rupt acknowledge cycles. Data is transferred
from the M II CPU during memory and I/O
write cycles.
Data setup and hold times must be met for
correct read cycle operation. The data bus is
driven only while a write cycle is active.
3.2.6
Data Parity
The Data Parity Bus (DP7-DP0) provides
and receives parity data for each of the eight
data bus bytes (Table 3-6). The M II CPU
generates even parity on the bus during write
cycles and accepts even parity from the system
during read cycles. DP7-DP0 is driven only
while a write cycle is active.
Parity Check (PCHK#) is asserted when a
data bus parity error is detected. Parity is
checked during code, memory and I/O reads,
and the second interrupt acknowledge cycle.
Parity is not checked during the first interrupt
acknowledge cycle.
Parity is checked for only the active data bytes
as determined by the active byte enable signals
except during a cache line fill (burst read or
“1+4” burst read). During a cache line fill, the
M II CPU assumes all data bytes are valid and
parity is checked for all data bytes regardless of
the state of the byte enables.
Table 3-6.
Parity Bit to Data
Byte Correlation
PARITY BIT
DATA BYTE
DP7
D63-D56
DP6
D55-D48
DP5
D47-D40
DP4
D39-D32
DP3
D31-D24
DP2
D23-D16
DP1
D15-D8
DP0
D7-D0
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