
Multifunctional Peripheral Controller 2000
MFC2000
100723A
Conexant
17-1
17. Bi-directional Parallel Peripheral Interface
The Parallel Peripheral Interface(PPI) controller incorporates the IEEE-1284 Compatibility/Nibble/ Byte/ ECP
protocols to offer flexible high-speed parallel data transfer. Furthermore, the PPI fully supports all variants of
these modes, including device ID requests and run-length encoded data compression. All protocols are signal-
compatible with classic parallel interfaces. The default protocol for the PPI is the Compatibility mode. The PPI
contains specific hardware to support automatic handshaking during host to peripheral,or forward, data transfers
in compatible and ECP modes, and run-length detection. The PPI also supports automatic handshaking during
peripheral to host, or reverse, data transfers in the Nibble, Byte and ECP modes. The hardware handshaking can
also be completely disabled to allow software to directly control the peripheral port interface signals and to
support new protocols as they arise in the future.
17.1 Operational Modes
The PPI supports three hardware handshaking modes for host to peripheral, or forward, data transfers. Each
mode can be enabled or disabled by software. One mode supports forward data transfers during compatibility
mode, and the other two modes support forward data transfers during ECP mode. Only one of the three modes
can be enabled at a time, or all modes can be disabled. When disabled, software must assume full responsibility
for handshaking, and use the Parallel Port Interface Register and the Parallel Port Data Register to read and
control the logic levels on all parallel port pins.
The hardware handshaking modes for peripheral to host, or reverse, data transfers are provided for Nibble, Byte
and ECP modes explained.
17.1.1 Compatibility Mode
The interface is always initialized to the compatibility Mode, a conventional, unidirectional host-to peripheral
interface. From the compatibility Mode the host may transmit data to peripheral or direct the interface to a mode
capable of transmitting data to the host. Compatibility mode hardware handshaking is enabled by setting the
MODE field to 1 in the Parallel Port Control Register. When compatibility mode is selected, the PPI interacts with
host using STROBEn, BUSY and ACKn signals.
17.1.2 P1284 Negotiation
The negotiation phase is performed under firmware control. During the negotiation, the firmware will respond to
the host stimulus by setting ACKn low, FAULTn high, SLCTOUT(XFlag) high, PE high as defined in the IEEE
1284 Specification. After the host responds to the prior signal setting, the firmware will respond with a PE low and
a FAULTn low if data to the host is available. The SLCTOUT is set to it’s appropriate value corresponding to the
extensibility feature requested by the host. (Refer to the IEEE 1284 Specification for a more complete definition of
this phase).
17.1.3 Nibble Mode
Provides an asynchronous, reverse (peripheral-to-host) channel, under control of the host. Data bytes are
transmitted as two sequential, four bit nibbles using four peripheral-to-host status lines. In Nibble
Mode(MODE=4), one byte of status data can be put to the PPI data register by CPU or DMA operation. The PPI
Logic will separate the one byte data into two nibbles and send them in sequence. The signals used in the Nibble
mode are AUTOFDn and ACKn for handshake and FAULTn, SLCTOUT, PE and BUSY for data transfer.
17.1.4 Byte Mode
Provides an asynchronous, byte-wide reverse peripheral-to-host channel using eight data lines of the interface for
data and the control/status lines for handshaking. The PPI hardware can control the handshake of the reverse
data transfer. The CPU must provide the status to send the next byte or to terminate the protocol. The MODE=5
for the Byte mode which enables a peripheral to send an entire byte of data to the PC in one data transfer cycle
using the 8 data lines, rather than the two cycles using the Nibble mode.The handshake signals are AUTOFDn,
ACKn and STROBEn.