
Hardware Description
MFC 2000 Multifunctional Peripheral Controller 2000
100723A
Conexant
4-73
4.6.2.3
NAND-Type Flash Memory
NAND type devices can only be used for data memory. NAND type flash devices have no address bus.
Command, address and data are passed through the external data bus. Accesses are accomplished by first
setting the appropriate flash CS and control signals through the FCSn[1:0] and GPIO pins. The actual bus transfer
is performed by accessing the
NANDFLSH
register. When accessing the
NANDFLSH
register, the appropriate
flash data strobe is activated, FRDn for read operations and FWRn for write. FRDn and FWRn are also controlled
by the wait state setting in the
FlashCtrl
register. The NAND-type bit in the
FlashCtrl
register must be 1.
FCSn[1:0]:
The device selection signals for the NAND type flash devices. FCS0n and FCS1n pins act as
GPO pins. FCSn[1:0] pins output values which are set to bit 8 and bit 9 of the FlashCtrl register.
Note:
GPO’s or GPIO’s can be used to generate FCS[1:0]n for NAND-type flash memory.
If FCS0n/PWM[1] and FCS1n/PWM[2] pins are programmed as PWM, any two available
FCLE:
The Flash Command Latch Enable. It is programmable via a GPIO pin. FCLE activates the commands
sent to the command register.
FALE:
The Flash Address Latch Enable. It is programmable via a GPIO pin. FALE activates the controls for
address or data to the internal address or data registers of the flash device.
FRDY:
The Flash Ready signal. It can be read from a GPIO pin. FRDY indicates the status of the flash device
operation.
FRDn:
The Flash Read Enable signal. It is a hardware generated signal. It is multiplexed on GPIO[1] and
configured in the GPIOConfig register. FRDn enables the data from the flash memory device onto its I/O bus.
This signal is active when the CPU reads the NAND flash location of 01FF8824h.
FWRn:
The Flash Write Enable signal. It is a hardware generated signal. It is multiplexed on GPIO[0] and
configured in the GPIOConfig register. FWRn controls writes to the I/O bus. This signal is active when the
CPU writes to the NAND flash location of 01FF8824h.
WRPROTn:
The write protect signal is driven low to protect the flash devices from inadvertent writes during
power transitions. It is also controlled by writing to the ‘Prime Power write protect’ bit (bit 11) of the FlashCtrl
register.
D[15:0]:
The external data bus.
Flash Address & Chip
Select Generator
(in SIU Block)
Flash Read/Write Control
ADDR[25:0]
FADD[20:0]
FCSn[1:0]
FRDn
FWRn
SIUCLK
RWn
Figure 4-30. Flash Control Block Diagram