
Hardware Description
MFC 2000 Multifunctional Peripheral Controller 2000
100723A
Conexant
11-5
11.2.2 Bit Packer
The Bit Packer block is responsible for performing the actual rotation of the image data. It accomplishes this task
by “picking” the bits out of the internal Bit Rotation RAM one bit at a time and packing them into the appropriate
format such that the final output image is rotated 90 degrees. The Bit Packer circuits also contain the bit counter
that describes the total number of printable bytes contained in the swath. The overall control of the print operation
is controlled by this block. The parameters that are required by this block are: the Line Length (LL), the Nozzle
Number (NN), the shuttle direction, and the packing order. In addition, this circuit also detects when there is an
underrun condition. An underrun condition occurs when the system is not able to keep up with the print rate.
Finally, the interface to the External Print ASIC is provided by this block.
11.2.3 Local Bit Rotation RAM
This memory is 512x16. Functionally, this memory consists of 2 banks of 256x16 memories, and only one of
these buffers is used at a time for rotating image memory data. The double-buffering is used for reasons of
system performance. When using the double-buffering mechanism, the system only needs to transfer the data at
a rate that corresponds to the print rate. This is due to the fact that while one bank is being loaded with swath
data, the other bank is being operated upon, or rotated and shipped to the External Print ASIC. This memory is
accessible by three resources: the SIU, the Swath Fetcher, and the Bit Packer. When a bit rotation operation is in
progress (when rotateStart in the ROTCTRL register is set to 1), then the SIU may not access this memory.
During this time, both the Swath Fetcher and the Bit Packer may access this memory, but not the same bank
simultaneously. When no bit rotation operation is in progress (the rotateStart bit is set to 0), then only the SIU has
access to this memory through address locations 01FF9000h-01FF93FFh.
11.2.4 BRB Local SRAM Memory Controller (brb_memif)
The brb_memif block is responsible for controlling all accesses to Local BRB SRAM. During Bit Rotation
operation, it will lock out all SIU accesses. At this time, it will allow both the Bit Packer and the Swath Fetcher
blocks to access the SRAM. The Swath Fetcher block is a write-only resource, and the Bit Packer is a read-only
resource. Arbitration to the SRAM by each of these resources is controlled with a rotating priority to ensure that
neither the Swath Fetcher or the Bit Packer get locked out for any length of time.
11.2.5 Control, Status, and Data Registers (brb_regs)
This block provides all required registers used in Bit Rotation operation. These registers are described in detail
later in section 11.3. The functional registers are spilt into two separate areas: Operation registers, and Setup
registers. The Operation registers are those registers that are meant for access during Bit Rotation. The Setup
registers are those register that are intended to be used once to set up the next print swath for printing. The
Operation registers for the Bit Rotation block are located at 01FF8060h-01FF806Fh, however, only locations
01FF8060h-01FF8063h are used. The Setup Registers are located at 01FF8870h-01FF888Fh, however, only
locations 01FF8870h-01FF8875h are used. The registers are summarized.
Register Address
Register Name
Summarized Description
01FF8060h
Rotation Control -
RotCtl
Provides programmability of parameters, initiates
Rotation, and provides status.
01FF8874h
Rotation Line Length -
RotLine
Contains the value of the line length in terms of
bytes.
01FF8870h
Nozzle Number -
RotNN
Provides programmability of number of nozzles on
inkjet head.
01FF8872h
BRB Warp -
BRBWarp
Provides programmability of swath warp in
increments of 32 bytes, up to 4096 bytes.
01FF8062h
Packing Register -
RotPack
Provides the data for the External Print ASIC