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參數(shù)資料
| 型號： | MC68HLC705KJ1 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Computer Operation Properly Module |
| 中文描述： | 電腦操作正確模塊 |
| 文件頁數(shù)： | 79/108頁 |
| 文件大?。?/td> | 718K |
| 代理商： | MC68HLC705KJ1 |
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MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
79
Chapter 9
Multifunction Timer Module
9.1 Introduction
The multifunction timer provides a timing reference with programmable real-time interrupt capability.
Figure 9-2
shows the timer organization.
9.2 Features
Features of the multifunction timer include:
Timer overflow
Four selectable interrupt rates
Computer operating properly (COP) watchdog timer
9.3 Operation
A 15-stage ripple counter, preceded by a prescaler that divides the internal clock signal by four, provides
the timing reference for the timer functions. The value of the first eight timer stages can be read at any
time by accessing the timer counter register at address $0009. A timer overflow function at the eighth
stage allows a timer interrupt every 1024 internal clock cycles.
The next four stages lead to the real-time interrupt (RTI) circuit. The RT1 and RT0 bits in the timer status
and control register at address $0008 allow a timer interrupt every 16,384, 32,768, 65,536, or 131,072
clock cycles. The last four stages drive the selectable COP system. For information on the COP, refer to
Chapter 3 Computer Operating Properly Module (COP)
.
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$0008
Timer Status and Control Register
(TSCR)
See page 81.
Read:
TOF
RTIF
TOIE
RTIE
0
0
RT1
RT0
Write:
TOFR
RTIFR
Reset:
0
0
0
0
0
0
1
1
$0009
Timer Counter Register
(TCR)
See page 82.
Read:
TMR7
TMR6
TMR5
TMR4
TMR3
TMR2
TMR1
TMR0
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-1. I/O Register Summary
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