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參數(shù)資料
| 型號(hào)： | MC68HLC705KJ1 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Computer Operation Properly Module |
| 中文描述： | 電腦操作正確模塊 |
| 文件頁(yè)數(shù)： | 68/108頁(yè) |
| 文件大小： | 718K |
| 代理商： | MC68HLC705KJ1 |
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Parallel I/O Ports (PORTS)
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
68
Freescale Semiconductor
7.3.3 Pulldown Register B
Pulldown register B inhibits the pulldown devices on port B pins programmed as inputs.
NOTE
If the SWPDI bit in the mask option register is programmed to logic 1, reset
initializes all port B pins as inputs with disabled pulldown devices.
PDIB[3:2] — Pulldown Inhibit B Bits
PDIB[3:2] disable the port B pulldown devices. Reset clears PDIB[3:2].
1 = Corresponding port B pulldown device disabled
0 = Corresponding port B pulldown device not disabled
Table 7-2. Port B Pin Operation
Data Direction Bit
I/O Pin Mode
Accesses to Data Bit
Read
Write
0
Input, high-impedance
Pin
Latch
(1)
1. Writing affects the data register, but does not affect input.
1
Output
Latch
Latch
Address:
$0011
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
See Note
PDIB3
PDIB2
See Note
Reset:
0
0
0
0
0
0
= Unimplemented
Note:
These pulldown devices are permanently enabled when PB5, PB4, PB1 and PB0 are con-
figured as inputs.
Figure 7-9. Pulldown Register B (PDRB)
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