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參數(shù)資料
| 型號： | MC68HLC705KJ1 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Computer Operation Properly Module |
| 中文描述： | 電腦操作正確模塊 |
| 文件頁數(shù)： | 59/108頁 |
| 文件大小： | 718K |
| 代理商： | MC68HLC705KJ1 |
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Effects of Stop and Wait Modes
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
59
6.3.3.1 STOP
The STOP instruction:
Clears the COP watchdog counter
Disables the COP watchdog clock
NOTE
To prevent the STOP instruction from disabling the COP watchdog,
program the stop-to-wait conversion bit (SWAIT) in the mask option register
to logic 1.
After exit from stop mode by external interrupt, the COP watchdog counter immediately begins counting
from $0000 and continues counting throughout the oscillator stabilization delay.
NOTE
Immediately after exiting stop mode by external interrupt, service the COP
to ensure a full COP timeout period.
After exit from stop mode by reset:
The COP watchdog counter immediately begins counting from $0000.
The COP watchdog counter is cleared at the end of the oscillator stabilization delay and begins
counting from $0000 again.
6.3.3.2 WAIT
The WAIT instruction has no effect on the COP watchdog.
NOTE
To prevent a COP timeout during wait mode, exit wait mode periodically to
service the COP.
6.3.4 Timer
Effects of STOP and WAIT on the timer are discussed here.
6.3.4.1 STOP
The STOP instruction:
Clears the RTIE, TOFE, RTIF, and TOF bits in the timer status and control register, disabling timer
interrupt requests and removing any pending timer interrupt requests
Disables the clock to the timer
After exiting stop mode by external interrupt, the timer immediately resumes counting from the last value
before the STOP instruction and continues counting throughout the oscillator stabilization delay.
After exiting stop mode by reset and after the oscillator stabilization delay, the timer resumes operation
from its reset state.
6.3.4.2 WAIT
The WAIT instruction has no effect on the timer.
6.3.5 EPROM/OTPROM
Effects of STOP and WAIT on the EPROM/OTPROM are discussed here.
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