參數(shù)資料
型號： MC68HLC705KJ1
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： Computer Operation Properly Module
中文描述： 電腦操作正確模塊
文件頁數(shù)： 51/108頁
文件大?。?/td> 718K
代理商： MC68HLC705KJ1
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
51
Chapter 5
External Interrupt Module (IRQ)
5.1 Introduction
The external interrupt (IRQ) module provides asynchronous external interrupts to the CPU. The following
sources can generate external interrupts:
IRQ/V
PP
pin
PA0–PA3 pins
5.2 Features
The external interrupt module (IRQ) includes these features:
Dedicated external interrupt pin (IRQ/V
PP
)
Selectable interrupt on four input/output (I/O) pins (PA0–PA3)
Programmable edge-only or edge- and level-interrupt sensitivity
5.3 Operation
The interrupt request/programming voltage pin (IRQ/V
PP
) and port A pins 0–3 (PA0–PA3) provide
external interrupts. The PIRQ bit in the mask option register (MOR) enables PA0–PA3 as IRQ interrupt
sources, which are combined into a single OR’ing function to be latched by the IRQ latch.
Figure 5-1
shows the structure of the IRQ module.
After completing its current instruction, the CPU tests the IRQ latch. If the IRQ latch is set, the CPU then
tests the I bit in the condition code register and the IRQE bit in the IRQ status and control register. If the
I bit is clear and the IRQE bit is set, the CPU then begins the interrupt sequence. This interrupt is serviced
by the interrupt service routine located at $07FA and $07FB.
The CPU clears the IRQ latch while it fetches the interrupt vector, so that another external interrupt
request can be latched during the interrupt service routine. As soon as the I bit is cleared during the return
from interrupt, the CPU can recognize the new interrupt request.
Figure 5-3
shows the sequence of events
caused by an interrupt.
5.3.1 IRQ/V
PP
Pin
An interrupt signal on the IRQ/V
PP
pin latches an external interrupt request. The LEVEL bit in the mask
option register provides negative edge-sensitive triggering or both negative edge-sensitive and low
level-sensitive triggering for the interrupt function.
If edge- and level-sensitive triggering is selected, a falling edge or a low level on the IRQ/V
PP
pin latches
an external interrupt request. Edge- and level-sensitive triggering allows the use of multiple wired-OR
external interrupt sources. An external interrupt request is latched as long as any source is holding the
IRQ/V
PP
pin low.
If level-sensitive triggering is selected, the IRQ/V
PP
input requires an external resistor to V
DD
for wired-OR
operation. If the IRQ/V
PP
pin is not used, it must be tied to the V
DD
supply.
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