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參數(shù)資料
| 型號(hào)： | MC68HLC705KJ1 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Computer Operation Properly Module |
| 中文描述： | 電腦操作正確模塊 |
| 文件頁(yè)數(shù)： | 27/108頁(yè) |
| 文件大?。?/td> | 718K |
| 代理商： | MC68HLC705KJ1 |
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Mask Option Register
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
27
2.8 Mask Option Register
The mask option register (MOR) is an EPROM/OTPROM byte that controls the following options:
COP watchdog (enable or disable)
External interrupt pin triggering (edge-sensitive only or edge- and level-sensitive)
Port A external interrupts (enable or disable)
Port pulldown resistors (enable or disable)
STOP instruction (stop mode or halt mode)
Crystal oscillator internal resistor (enable or disable)
EPROM security (enable or disable)
Short oscillator delay (enable or disable)
Take the following steps to program the mask option register (MOR):
1.
Apply the programming voltage, V
PP
, to the IRQ/V
PP
pin.
2.
Write to the MOR.
3.
Set the MPGM bit and wait for a time, t
MPGM
.
4.
Clear the MPGM bit.
5.
Reset the MCU.
SOSCD — Short Oscillator Delay Bit
The SOSCD bit controls the oscillator stabilization counter. The normal stabilization delay following
reset or exit from stop mode is 4064 t
cyc
. Setting SOSCD enables a 128 t
cyc
stabilization delay.
1 = Short oscillator delay enabled
0 = Short oscillator delay disabled
EPMSEC — EPROM Security Bit
The EPMSEC bit controls access to the EPROM/OTPROM.
1 = External access to EPROM/OTPROM denied
0 = External access to EPROM/OTPROM not denied
OSCRES — Oscillator Internal Resistor Bit
The OSCRES bit enables a 2-M
internal resistor in the oscillator circuit.
1 = Oscillator internal resistor enabled
0 = Oscillator internal resistor disabled
NOTE
Program the OSCRES bit to logic 0 in devices using low-speed crystal or
RC oscillators with external resistor.
Address:
$07F1
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SOSCD
EPMSEC
OSCRES
SWAIT
SWPDI
PIRQ
LEVEL
COPEN
Write:
Reset:
Unaffected by reset
Figure 2-4. Mask Option Register (MOR)
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