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參數(shù)資料
| 型號： | MC68HLC705KJ1 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Computer Operation Properly Module |
| 中文描述： | 電腦操作正確模塊 |
| 文件頁數(shù)： | 28/108頁 |
| 文件大?。?/td> | 718K |
| 代理商： | MC68HLC705KJ1 |
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Memory
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
28
Freescale Semiconductor
SWAIT — Stop-to-Wait Conversion Bit
The SWAIT bit enables halt mode. When the SWAIT bit is set, the CPU interprets the STOP instruction
as a WAIT instruction, and the MCU enters halt mode. Halt mode is the same as wait mode, except
that an oscillator stabilization delay of 1 to 4064 t
cyc
occurs after exiting halt mode.
1 = Halt mode enabled
0 = Halt mode not enabled
SWPDI — Software Pulldown Inhibit Bit
The SWPDI bit inhibits software control of the I/O port pulldown devices. The SWPDI bit overrides the
pulldown inhibit bits in the port pulldown inhibit registers.
1 = Software pulldown control inhibited
0 = Software pulldown control not inhibited
PIRQ — Port A External Interrupt Bit
The PIRQ bit enables the PA0–PA3
pins to function as external interrupt pins.
1 = PA0–PA3 enabled as external interrupt pins
0 = PA0–PA3 not enabled as external interrupt pins
LEVEL —External Interrupt Sensitivity Bit
The LEVEL bit controls external interrupt triggering sensitivity.
1 = External interrupts triggered by active edges and active levels
0 = External interrupts triggered only by active edges
COPEN — COP Enable Bit
The COPEN bit enables the COP watchdog.
1 = COP watchdog enabled
0 = COP watchdog disabled
2.9 EPROM Programming Characteristics
Table 2-1. EPROM Programming Characteristics
(1)
1. V
DD
= 5.0 Vdc
±
10%, V
SS
= 0 Vdc, T
A
= –40
°
C to +85
°
C
Characteristic
Symbol
Min
Typ
Max
Unit
Programming Voltage
IRQ/V
PP
Programming Current
IRQ/V
PP
V
PP
16.0
16.5
17.0
V
I
PP
—|
3.0
10.0
mA
Programming Time
Per Array Byte
MOR
t
EPGM
t
MPGM
4
4
—
—
—
—
ms
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