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參數(shù)資料
| 型號： | MC68HLC705KJ1 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Computer Operation Properly Module |
| 中文描述： | 電腦操作正確模塊 |
| 文件頁數(shù)： | 66/108頁 |
| 文件大?。?/td> | 718K |
| 代理商： | MC68HLC705KJ1 |
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Parallel I/O Ports (PORTS)
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
66
Freescale Semiconductor
7.2.4 Port LED Drive Capability
All outputs can drive light-emitting diodes (LEDs). These pins can sink approximately 10 mA of current to
V
SS
.
7.2.5 Port A I/O Pin Interrupts
If the PIRQ bit in the mask option register is programmed to logic 1, PA0–PA3 pins function as external
interrupt pins. (See
Chapter 5 External Interrupt Module (IRQ)
.)
7.3 Port B
Port B is a 2-bit bidirectional port.
7.3.1 Port B Data Register
The port B data register contains a latch for each port B pin.
PB[3:2] — Port B Data Bits
These read/write bits are software programmable. Data direction of each port B pin is under the control
of the corresponding bit in data direction register B. Reset has no effect on port B data.
NOTE
PB4–PB5 and PB0–PB1 should be configured as inputs at all times. These
bits are available for read/write but are not available externally. Configuring
them as inputs will ensure that the pulldown devices are enabled, thus
properly terminating them.
Address:
$0001
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
See Note
PB3
PB2
See Note
Write:
Reset:
Unaffected by reset
= Unimplemented
Note:
PB5, PB4, PB1, and PB0 should be configured as inputs at all times. These bits are avail-
able for read/write but are not available externally. Configuring them as inputs will ensure
that the pulldown devices are enabled, thus properly terminating them.
Figure 7-6. Port B Data Register (PORTB)
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