參數(shù)資料
型號(hào)： MC68HLC705KJ1
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Computer Operation Properly Module
中文描述： 電腦操作正確模塊
文件頁(yè)數(shù)： 54/108頁(yè)
文件大?。?/td> 718K
代理商： MC68HLC705KJ1
External Interrupt Module (IRQ)
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
54
Freescale Semiconductor
If edge- and level-sensitive triggering is selected, a rising edge or a high level on a PA0–PA3 pin latches
an external interrupt request. Edge- and level-sensitive triggering allows the use of multiple wired-OR
external interrupt sources. As long as any source is holding a PA0–PA3 pin high, an external interrupt
request is latched, and the CPU continues to execute the interrupt service routine.
If edge-sensitive only triggering is selected, a rising edge on a PA0–PA3 pin latches an external interrupt
request. A subsequent external interrupt request can be latched only after the voltage level of the previous
interrupt signal returns to logic 0 and then rises again to logic 1.
NOTE
The BIH and BIL instructions apply only to the level on the IRQ/V
PP
pin itself
and not to the output of the logic OR function with the PA0
–
PA3 pins. The
state of the individual port A pins can be checked by reading the
appropriate port A pins as inputs.
Enabled PA0
–
PA3 pins cause an IRQ interrupt regardless of whether these
pins are configured as inputs or outputs.
The IRQ pin has an internal Schmitt trigger. The optional external interrupts
(PA0
–
PA3) do not have internal Schmitt triggers.
The interrupt mask bit (I) in the condition code register (CCR) disables all
maskable interrupt requests, including external interrupt requests.
5.4 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. All unused
bits in the ISCR read as logic 0s. The IRQF bit is cleared and the IRQE bit is set by reset.
IRQR — Interrupt Request Reset Bit
This write-only bit clears the external interrupt request flag.
1 = Clears external interrupt and IRQF bit
0 = No effect on external interrupt and IRQF bit
IRQF — External Interrupt Request Flag
The external interrupt request flag is a clearable, read-only bit that is set when an external interrupt
request is pending. Reset clears the IRQF bit.
1 = External interrupt request pending
0 = No external interrupt request pending
IRQE — External Interrupt Request Enable Bit
This read/write bit enables external interrupts. Reset sets the IRQE bit.
1 = External interrupt requests enabled
0 = External interrupt requests disabled
Address:
$000A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
IRQE
0
0
0
IRQF
0
0
0
Write:
R
IRQR
Reset:
1
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Figure 5-4. IRQ Status and Control Register (ISCR)
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