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參數(shù)資料
| 型號： | MC68HLC705KJ1 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Computer Operation Properly Module |
| 中文描述： | 電腦操作正確模塊 |
| 文件頁數(shù)： | 19/108頁 |
| 文件大?。?/td> | 718K |
| 代理商： | MC68HLC705KJ1 |
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Pin Functions
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
19
1.4.2.4 External Clock
An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the
OSC2 input not connected, as shown in
Figure 1-8
. This configuration is possible regardless of whether
the crystal/ceramic resonator or the RC oscillator is enabled.
Figure 1-8. External Clock Connections
1.4.3 RESET
Applying a logic 0 to the RESET pin forces the MCU to a known startup state. An internal reset also pulls
the RESET pin low. An internal resistor to V
DD
pulls the RESET pin high. A steering diode between the
RESET and V
DD
pins discharges any RESET pin voltage when power is removed from the MCU. The
RESET pin contains an internal Schmitt trigger to improve its noise immunity as an input. Refer to
Chapter 8 Resets and Interrupts
for more information.
1.4.4 IRQ/V
PP
The external interrupt/programming voltage pin (IRQ/V
PP
) drives the asynchronous IRQ interrupt function
of the CPU. Additionally, it is used to program the user EPROM and mask option register. (See
Chapter 2 Memory
and
Chapter 5 External Interrupt Module (IRQ)
.)
The LEVEL bit in the mask option register provides negative edge-sensitive triggering or both negative
edge-sensitive and low level-sensitive triggering for the interrupt function.
If level-sensitive triggering is selected, the IRQ/V
PP
input requires an external resistor to V
DD
for wired-OR
operation. If the IRQ/V
PP
pin is not used, it must be tied to the V
DD
supply.
The IRQ/V
PP
pin contains an internal Schmitt trigger as part of its input to improve noise immunity. The
voltage on this pin should not exceed V
DD
except when the pin is being used for programming the
EPROM.
NOTE
The mask option register can enable the PA0
–
PA3
pins to function as
external interrupt pins.
1.4.5 PA0–PA7
These eight input/output (I/O) lines comprise port A, a general-purpose bidirectional I/O port. (See
Chapter 5 External Interrupt Module (IRQ)
for information on PA0–PA3 external interrupts.)
1.4.6 PB2 and PB3
These two I/O lines comprise port B, a general-purpose bidirectional I/O port.
MCU
EXTERNAL
CMOS CLOCK
O
O
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