參數(shù)資料
型號(hào)： MC68HLC705KJ1
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Computer Operation Properly Module
中文描述： 電腦操作正確模塊
文件頁(yè)數(shù)： 30/108頁(yè)
文件大?。?/td> 718K
代理商： MC68HLC705KJ1
Computer Operating Properly Module (COP)
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
30
Freescale Semiconductor
3.3.3 Clearing the COP Watchdog
To clear the COP watchdog and prevent a COP reset, write a logic 0 to bit 0 (COPC) of the COP register
at location $07F0
(see
Figure 3-1
). Clearing the COP bit disables the COP watchdog timer regardless of
the IRQ/V
PP
pin voltage.
If the main program executes within the COP timeout period, the clearing routine should be executed only
once. If the main program takes longer than the COP timeout period, the clearing routine must be
executed more than once.
NOTE
Place the clearing routine in the main program and not in an interrupt
routine. Clearing the COP watchdog in an interrupt routine might prevent
COP watchdog timeouts even though the main program is not operating
properly.
3.4 Interrupts
The COP watchdog does not generate interrupts.
3.5 COP Register
The COP register (COPR) is a write-only register that returns the contents of EPROM location $07F0
when read.
COPC — COP Clear Bit
This write-only bit resets the COP watchdog. Reading address $07F0 returns undefined results.
3.6 Low-Power Modes
The STOP and WAIT instructions have the following effects on the COP watchdog.
3.6.1 Stop Mode
The STOP instruction clears the COP watchdog counter and disables the clock to the COP watchdog.
NOTE
To prevent the STOP instruction from disabling the COP watchdog,
program the stop-to-wait conversion bit (SWAIT) in the mask option register
to logic 1.
Address:
$07F0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
COPC
Reset:
U
U
U
U
U
U
U
0
= Unimplemented
U = Unaffected
Figure 3-1. COP Register (COPR)
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