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參數(shù)資料
| 型號： | MC68HLC705KJ1 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Computer Operation Properly Module |
| 中文描述： | 電腦操作正確模塊 |
| 文件頁數(shù)： | 72/108頁 |
| 文件大?。?/td> | 718K |
| 代理商： | MC68HLC705KJ1 |
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Resets and Interrupts
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
72
Freescale Semiconductor
8.2.1 Power-On Reset
A positive transition on the V
DD
pin generates a power-on reset.
NOTE
The power-on reset is strictly for power-up conditions and cannot be used
to detect drops in power supply voltage.
A 4064-t
cyc
(internal clock cycle) delay after the oscillator becomes active allows the clock generator to
stabilize. If any reset source is active at the end of this delay, the MCU remains in the reset condition until
all reset sources are inactive.
Figure 8-2. Power-On Reset Timing
8.2.2 External Reset
A logic 0 applied to the RESET pin for 1 1/2 t
cyc
generates an external reset. A Schmitt trigger senses the
logic level at the RESET pin.
Figure 8-3. External Reset Timing
Table 8-1. External Reset Timing
Characteristic
Symbol
Min
Max
Unit
RESET Pulse Width
t
RL
1.5
—
t
cyc
OSCILLATOR STABILIZATION DELAY
(2)
V
DD
OSC1 PIN
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
Notes:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. 4064 cycles or 128 cycles, depending on state of SOSCD bit in MOR
3. Internal clock, internal address bus, and internal data bus are not available externally.
INTERNAL
DATA BUS
$07FE
$07FE
$07FE
$07FE
$07FE
$07FE
$07FF
NEWPCH
NEWPCL
(NOTE 1)
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
Notes:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
INTERNAL
DATA BUS
$07FE
$07FE
$07FE
$07FE
$07FF
NEW PC
NEW
PCH
t
RL
NEW PC
NEW
PCL
DUMMY
OP
CODE
RESET
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