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| 型號(hào)： | MC68HC05SB7 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | MO-150, SSOP-28 |
| 文件頁(yè)數(shù)： | 5/170頁(yè) |
| 文件大小： | 2161K |
| 代理商： | MC68HC05SB7 |
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GENERAL RELEASE SPECIFICATION
August 27, 1998
MOTOROLA
ANALOG SUBSYSTEM
MC68HC05SB7
15-4
REV 2.1
NOTE
When sampling a voltage for later conversion the HOLD and DHOLD bit should be
cleared before making any changes in the MUX channel selection. If the MUX
channel and the HOLD/DHOLD are changed on the same write cycle to the
AMUX1 register, the sampled voltage may be altered during the channel
switching.
INV
This is a read/write bit that controls the phase of the voltage comparator. This
bit allows voltage comparisons with either input node of the voltage comparator
to be presented to the rest of the circuit as the “positive” or “negative” input.
The voltage comparator is dened as non-inverted when the internal positive
node is connected to the external positive input and the output is not inverted.
In this case the output will go to a logical one when the voltage on the positive
input is higher than the voltage on the negative input. Any input offset voltage in
the voltage comparator will be with respect to the negative input.
The voltage comparator is dened as inverted when the internal negative node
is connected to the external positive input and the output is inverted. In this
case the output will still go to a logical one when the voltage on the positive
input is higher than the voltage on the negative input. In the inverted case any
input offset voltage in the voltage comparator will be with respect to the positive
input. This bit is cleared by a reset of the device.
1 =
The voltage comparator is internally inverted.
0 =
The voltage comparator is not internally inverted.
Figure 15-4. INV Bit Action
NOTE
The effect of changing the state of the INV bit is to only change the polarity of the
input offset voltage. It does not change the output phase of the CPF ag with
respect to the external port pins.
The comparator may generate an output ag when the inputs are exchanged due
to a change in the state of the INV bit. It is therefore recommended that the INV bit
–
+
COMP
VIO
V+
V–
INV=0
RISE
WHEN
V+ > V–
–
+
COMP
VIO
V+
V–
INV=1
RISE
WHEN
V+ > V–
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