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參數(shù)資料
| 型號： | MC68HC05SB7 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | MO-150, SSOP-28 |
| 文件頁數(shù)： | 152/170頁 |
| 文件大?。?/td> | 2161K |
| 代理商： | MC68HC05SB7 |
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GENERAL RELEASE SPECIFICATION
August 27, 1998
MOTOROLA
SM-BUS
MC68HC05SB7
12-4
REV 2.1
Each data byte is 8 bits long. Data can be changed only when SCL is low and
must be held stable when SCL high as shown in Figure 12-2. The MSB is trans-
mitted rst and each byte has to be followed by an acknowledge bit. This is sig-
nalled by the receiving device by pulling the SDA low on the 9th clock cycle.
Therefore one complete data byte transfer needs 9 clock cycles.
If the slave receiver does not acknowledge the master, the SDA line should be left
high by the slave. The master can then generate a STOP signal to abort the data
transfer or a START signal (repeated start) to commence a new transfer.
If the master receiver does not acknowledge the slave transmitter after a byte has
been transmitted, it means an “end of data” to the slave. The slave should now
release the SDA line for the master to generate a “STOP” or “START” signal.
12.4.4 Repeated START Signal
As shown in Figure 12-2, a repeated START signal is used to generate a START
signal without rst generating a STOP signal to terminate the communication. This
is used by the master to communicate with another slave or with the same slave in
a different mode (transmit/receive mode) without releasing the bus.
12.4.5 STOP Signal
With reference to Figure 12-2, the master can terminate the communication by
generating a STOP signal to free the bus. However, the master may generate a
START signal followed by a calling command without rst generating a STOP sig-
nal. This is called repeat start. A STOP signal is dened as a low to high transition
of SDA while SCL is at logical high.
12.4.6 Arbitration Procedure
This interface circuit is a true multi-master system which allows more than one
master to be connected to it. If two or more masters try to control the bus at the
same time, a clock synchronization procedure determines the bus clock, for which
the low period is equal to the longest clock low period and the high is equal to the
shortest one among the masters. A data arbitration procedure determines the pri-
ority. The masters will lose arbitration if they transmit logic “1” while another trans-
mits logic “0”. The losing masters will immediately switch over to slave receive
mode and stop its data and clock outputs. The transition from master to slave
mode will not generate a STOP condition in this case. Meanwhile a software bit
will be set by hardware to indicate loss of arbitration.
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