參數(shù)資料
型號: MC68HC05SB7
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: MO-150, SSOP-28
文件頁數(shù): 129/170頁
文件大?。?/td> 2161K
代理商: MC68HC05SB7
August 27, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05SB7
CORE TIMER
MOTOROLA
REV 2.1
9-5
COPON — COP ON
COPON is a write-once bit.
1 =
Enables COP watchdog system.
0 =
No effect on system.
NOTE
If the voltage on the IRQ/VPP pin exceeds 2 × VDD, the COP watchdog is disabled,
and remains disabled until the IRQ/VPP voltage falls below 2 × VDD.
9.4
CORE TIMER DURING WAIT MODE
The CPU clock halts during the WAIT mode, but the timer remains active. If the
interrupts are enabled, the timer interrupt will cause the processor to exit the WAIT
mode.
9.5
CORE TIMER DURING STOP MODE
The Core Timer is cleared when going into STOP mode. When STOP is exited by
an external interrupt or an external RESET, the internal oscillator will resume, fol-
lowed by 4064 cycles internal processor stabilization delay. The timer is then
cleared and operation resumes.
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