參數(shù)資料
型號(hào): MC68HC05SB7
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: MO-150, SSOP-28
文件頁數(shù): 110/170頁
文件大小: 2161K
代理商: MC68HC05SB7
GENERAL RELEASE SPECIFICATION
August 27, 1998
MOTOROLA
RESETS
MC68HC05SB7
5-6
REV 2.1
A reset therefore disables the SM-Bus and leaves the shared port A pins as gen-
eral I/O. Any pending interrupt ag is cleared and the SM-Bus interrupt is dis-
abled. Also the clock rate defaults to the fastest rate.
5.4.7 Analog Subsystem
A reset has the following effects on the analog subsystem:
Clears all the bits in the multiplex registers (AMUX1, AMUX2) bits except
the hold switch bit (HOLD) which is set.
Clears all the bits in the analog control register (ACR).
Clears all the bits in the analog status register (ASR).
A reset therefore connects the negative input of comparator to the channel selec-
tion bus, which is switched to VSS. The comparator is set up as non-inverting (a
higher positive voltage on the positive input results in a positive output) and both
are powered down. The current source and discharge device on the CAP pin is
also disabled and powered down. Any analog subsystem interrupt ags are
cleared and the interrupts are disabled.
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