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| 型號(hào)： | MC68HC05SB7 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | MO-150, SSOP-28 |
| 文件頁(yè)數(shù)： | 163/170頁(yè) |
| 文件大?。?/td> | 2161K |
| 代理商： | MC68HC05SB7 |
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GENERAL RELEASE SPECIFICATION
August 27, 1998
MOTOROLA
SM-BUS
MC68HC05SB7
12-14
REV 2.1
12.6.5 Generation of a Repeated START Signal
If at the end of data transfer the master still wants to communicate on the bus, it
can generate another START signal followed by another slave address without
rst generating a STOP signal. A program example is shown below.
RESTART
BCLR
5,SMCR
; ANOTHER START (RESTART) IS
BSET
5,SMCR
; GENERATED BY THESE TWO
; CONSEQUENCE INSTRUCTION
LDA
#CALLING
; GET THE CALLING ADDRESS
STA
SMDR
; TRANSMIT THE CALLING ADDRESS
12.6.6 Slave Mode
In the slave service routine, the master addressed as slave bit (SMAAS) should
be tested to see if a calling of its own address has just been received. If SMAAS is
set, software should set the transmit/receive mode select bit (SMTX bit of SMCR)
according to the R/W-command bit (SRW). Writing to the SMCR clears the
SMAAS automatically. A data transfer may then be initiated by writing information
to SMDR or dummy reading from SMDR.
In the slave transmitter routine, the received acknowledge bit (RXAK) must be
tested before transmitting the next byte of data. If RXAK is set, indicating an “end
of data” signal from the master receiver, then it must switch from transmitter mode
to receiver mode by software and a dummy read must follow to release the SCL
line so that the master can generate a stop signal.
12.6.7 Arbitration Lost
If more than one master want to acquire the bus simultaneously, only one master
wins and the others lost arbitration. The arbitration lost devices immediately switch
to slave receive mode by hardware. Their data output to the SDA line is stopped,
but internal transmitting clock still run until the end of the byte transmitting. An
interrupt occurs when this dummy “byte” transmitting is accomplished with
SMAL=1 and SMSTA = 0. If one master attempt to start transmission while the
bus is being engaged by another master, the hardware will inhibit the transmis-
sion; switch the SMSTA bit from 1 to 0 without generating STOP condition; gener-
ate an interrupt to CPU and set the SMAL to indicate that the attempt to engage
the bus is failed. Consideration of these cases, the slave service routine should
test the SMAL rst, software should clear the SMAL bit if it is set.
12.7
OPERATION DURING WAIT MODE
During WAIT mode the SM-Bus block is idle. If in slave mode it will wake up on
receiving a valid start condition. If the interrupt is enabled the CPU will come out
of WAIT mode after the end of a byte transmission.
12.8
OPERATION DURING STOP MODE
In Stop Mode the SM-Bus is disabled.
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