參數(shù)資料
型號(hào): MC68HC05SB7
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: MO-150, SSOP-28
文件頁(yè)數(shù): 126/170頁(yè)
文件大?。?/td> 2161K
代理商: MC68HC05SB7
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August 27, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05SB7
CORE TIMER
MOTOROLA
REV 2.1
9-3
RTIFR — Real-Time Interrupt Flag Reset
Writing a logic one to this write only bit clears the RTIF bit. RTIFR always reads
as a logic zero. Reset does not affect RTIFR.
1 =
Clear RTIF ag bit.
0 =
No effect on RTIF ag bit.
RT1, RT0 — Real-Time Interrupt Select Bits 1 and 0
These read/write bits select one of four real time interrupt rates, as shown in
Table 9-1. Because the selected RTI output drives the COP watchdog, chang-
ing the real time interrupt rate also changes the counting rate of the COP
watchdog. Reset sets RT1 and RT0, selecting the longest COP timeout period
and real-time interrupt period.
NOTE
Changing RT1 and RT0 when a COP timeout is imminent or uncertain may cause
a real time interrupt request to be missed or an additional real time interrupt
request to be generated. Therefore, the COP timer should be cleared (by writing a
just before changing RT1 and RT0.
9.2
CORE TIMER COUNTER REGISTER (CTCR)
A 15-stage ripple counter is the basis of the Core Timer. The value of the rst eight
stages is readable at any time from the read only timer counter register as shown
Table 9-1. Core Timer Interrupt Rates and COP Timeout Selection
Timer Overflow Interrupt
(TOF) Period (fOP ÷ 2
10)
RT1
RT0
RTI Rate
Real-Time Interrupt
(RTI) Period
Minimum COP
Timeout Period
(7 or 8 RTI Periods)
fOP =
2.1 MHz
fOP =
1.0 MHz
fOP =
2.1 MHz
fOP =
1.0 MHz
fOP =
2.1 MHz
fOP =
1.0 MHz
488
s
1024
s
00
fOP ÷ 2
14
7.81 ms
16.4 ms
54.7 ms
114 ms
01
fOP ÷ 2
15
15.6 ms
32.8 ms
109 ms
229 ms
10
fOP ÷ 2
16
31.3 ms
65.5 ms
219 ms
458 ms
11
fOP ÷ 2
17
62.5 ms
131 ms
438 ms
916 ms
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CTCR
R
TMR7
TMR6
TMR5
TMR4
TMR3
TMR2
TMR1
TMR0
$0009
W
reset:
00000000
Figure 9-3. Core Timer Counter Register (CTCR)
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