參數(shù)資料
    型號: MC68HC05SB7
    廠商: FREESCALE SEMICONDUCTOR INC
    元件分類: 微控制器/微處理器
    英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
    封裝: MO-150, SSOP-28
    文件頁數(shù): 16/170頁
    文件大?。?/td> 2161K
    代理商: MC68HC05SB7
    GENERAL RELEASE SPECIFICATION
    August 27, 1998
    MOTOROLA
    ANALOG SUBSYSTEM
    MC68HC05SB7
    15-14
    REV 2.1
    X = Don’t Care
    Z
    = High Impedance
    15.2
    ANALOG CONTROL REGISTER
    The Analog Control Register (ACR) controls the power up, interrupt and ag oper-
    ation. The analog subsystem draws about 470
    A of current while it is operating.
    The resulting power consumption can be reduced by powering down the analog
    subsystem when not in use. This can be done by clearing two enable bits (ISEN
    and CPEN) in the ACR at $001D. Since these bits are cleared following a reset,
    the voltage comparator and the charge current source will be powered down fol-
    lowing a reset of the device.
    The control bits in the ACR are shown in Figure 15-2. All the bits in this register
    are cleared by a reset of the device.
    X
    11110111
    Z
    ON
    Z
    ON
    Z
    X
    11111000
    Z
    ON
    ZZZZ
    X
    11111001
    Z
    ON
    Z
    ON
    Z
    X
    11111010
    Z
    ON
    Z
    ON
    Z
    X
    11111011
    Z
    ON
    Z
    ON
    Z
    X
    11111100
    Z
    ON
    Z
    X
    11111101
    Z
    ON
    Z
    ON
    Z
    X
    11111110
    Z
    ON
    Z
    X
    11111111
    Z
    ON
    Z
    0100000000
    Z
    ON
    ZZZZZZZZZ
    1000000000
    ON
    ZZZZZZZZZZ
    BIT 7
    BIT 6
    BIT 5
    BIT 4
    BIT 3
    BIT 2
    BIT 1
    BIT 0
    ACR
    R
    CHG
    ATD2
    ATD1
    ICEN
    CPIE
    CPEN
    ISEN
    $001D
    W
    reset:
    00000000
    Figure 15-5. Analog Control Register (ACR)
    Table 15-2. Channel Select Bus Combinations
    Analog Multiplex Registers
    (AMUX1 and AMUX2)
    Channel Select Bus Connected to:
    V
    R
    E
    F
    I
    B
    R
    E
    F
    M
    U
    X
    7
    M
    U
    X
    6
    M
    U
    X
    5
    M
    U
    X
    4
    M
    U
    X
    3
    M
    U
    X
    2
    M
    U
    X
    1
    M
    U
    X
    0
    VDD
    VIB
    AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
    VSS
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