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參數(shù)資料
| 型號： | MC68HC05SB7 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | MO-150, SSOP-28 |
| 文件頁數(shù)： | 102/170頁 |
| 文件大?。?/td> | 2161K |
| 代理商： | MC68HC05SB7 |
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August 27, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05SB7
INTERRUPTS
MOTOROLA
REV 2.1
4-7
4.5.1 Core Timer Overow Interrupt
An overow interrupt request occurs if the Core Timer overow ag (TOF)
becomes set while the Core Timer overow interrupt enable bit (TOFE) is also set.
The TOF ag bit can be reset by writing a logical one to the CTOFR bit in the
CTSCR or by a reset of the device.
4.5.2 Real-Time Interrupt
A real-time interrupt request occurs if the real-time interrupt ag (RTIF) becomes
set while the real-time interrupt enable bit (RTIE) is also set. The RTIF ag bit can
be reset by writing a logical one to the RTIFR bit in the CTSCR or by a reset of the
device.
4.6
PROGRAMMABLE TIMER INTERRUPTS
The 16-bit programmable Timer can generate an interrupt whenever the following
events occur:
Input capture.
Output compare.
Timer counter overow.
Setting the I bit in the condition code register disables Timer interrupts. The con-
trols for these interrupts are in the Timer control register (TCR) located at $0012
and in the status bits are in the Timer status register (TSR) located at $0013.
4.6.1 Input Capture Interrupt
An input capture interrupt occurs if the input capture ag (ICF) becomes set while
the input capture interrupt enable bit (ICIE) is also set. The ICF ag bit is in the
TSR; and the ICIE enable bit is located in the TCR. The ICF ag bit is cleared by a
read of the TSR with the ICF ag bit is set; and then followed by a read of the LSB
of the input capture register (ICRL) or by reset. The ICIE enable bit is unaffected
by reset.
4.6.2 Output Compare Interrupt
An output compare interrupt occurs if the output compare ag (OCF) becomes set
while the output compare interrupt enable bit (OCIE) is also set. The OCF ag bit
is in the TSR and the OCIE enable bit is in the TCR. The OCF ag bit is cleared by
a read of the TSR with the OCF ag bit set; and then followed by an access to the
LSB of the output compare register (OCRL) or by reset. The OCIE enable bit is
unaffected by reset.
4.6.3 Timer Overow Interrupt
A Timer overow interrupt occurs if the Timer overow ag (TOF) becomes set
while the Timer overow interrupt enable bit (TOIE) is also set. The TOF ag bit is
in the TSR and the TOIE enable bit is in the TCR. The TOF ag bit is cleared by a
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