參數(shù)資料
型號: MC68HC05SB7
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: MO-150, SSOP-28
文件頁數(shù): 141/170頁
文件大?。?/td> 2161K
代理商: MC68HC05SB7
GENERAL RELEASE SPECIFICATION
August 27, 1998
MOTOROLA
16-BIT TIMER
MC68HC05SB7
10-10
REV 2.1
OLVL - OUTPUT COMPARE OUTPUT LEVEL SELECT
The state of this read/write bit determines whether a logic one or a logic zero
appears on the TCMP when a successful output compare occurs. Reset clears
the OLVL bit.
1 =
TCMP goes high on output compare.
0 =
TCMP goes low on output compare.
10.6
TIMER STATUS REGISTER (TSR)
The timer status register (TSR) shown in Figure 10-13 contains ags for the fol-
lowing events:
An active signal on the PB1/TCAP pin or the CPF ag bit of voltage
comparator in the analog subsystem, transferring the contents of the
timer registers to the input capture registers.
A match between the 16-bit counter and the output compare registers,
transferring the OLVL bit to the TCMP.
An overow of the timer registers from $FFFF to $0000.
Writing to any of the bits in the TSR has no effect. Reset does not change the
state of any of the ag bits in the TSR.
ICF - INPUT CAPTURE FLAG
The ICF bit is automatically set when an edge of the selected polarity occurs on
the PB1/TCAP pin. Clear the ICF bit by reading the timer status register with
the ICF set, and then reading the low byte (ICRL, $0015) of the input capture
registers. Reset has no effect on ICF.
OCF - OUTPUT COMPARE FLAG
The OCF bit is automatically set when the value of the timer registers matches
the contents of the output compare registers. Clear the OCF bit by reading the
timer status register with the OCF set, and then accessing the low byte (OCRL,
$0017) of the output compare registers. Reset has no effect on OCF.
TOF - TIMER OVERFLOW FLAG
The TOF bit is automatically set when the 16-bit timer counter rolls over from
$FFFF to $0000. Clear the TOF bit by reading the timer status register with the
TOF set, and then accessing the low byte (TMRL, $0019) of the timer registers.
Reset has no effect on TOF.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TSR
R
ICF
OCF
TOF
00000
$0013
W
reset:
U
00000
U = UNAFFECTED BY RESET
Figure 10-13. Timer Status Registers (TSR)
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