參數(shù)資料
型號: MC68HC05SB7
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: MO-150, SSOP-28
文件頁數(shù): 125/170頁
文件大小: 2161K
代理商: MC68HC05SB7
GENERAL RELEASE SPECIFICATION
August 27, 1998
MOTOROLA
CORE TIMER
MC68HC05SB7
9-2
REV 2.1
9.1
CORE TIMER STATUS AND CONTROL REGISTER
The read/write Core Timer status and control register contains the interrupt ag
bits, interrupt enable bits, interrupt ag bit resets, and the rate selects for the real
time interrupt as shown in Figure 9-2.
CTOF — Core Timer Overow Flag
This read only ag becomes set when the rst eight stages of the Core Timer
counter roll over from $FF to $00. The CTOF ag bit generates a timer overow
interrupt request if CTOFE is also set. The CTOF ag bit is cleared by writing a
logic one to the CTOFR bit. Writing to CTOF has no effect. Reset clears CTOF.
1 =
Overow in Core Timer has occurred.
0 =
No overow of Core Timer since CTOF last cleared.
RTIF — Real Time Interrupt Flag
This read only ag becomes set when the selected RTI output becomes active.
RTIF generates a real time interrupt request if RTIE is also set. The RTIF
enable bit is cleared by writing a logic one to the RTIFR bit. Writing to RTIF has
no effect. Reset clears RTIF.
1 =
Overow in real time counter has occurred.
0 =
No overow of real time counter since RTIF last cleared.
CTOFE — Core Timer Overow Interrupt Enable
This read/write bit enables Core Timer overow interrupts. Reset clears
CTOFE.
1 =
Core Timer overow interrupts enabled.
0 =
Core Timer overow interrupts disabled.
RTIE — Real-Time Interrupt Enable
This read/write bit enables real time interrupts. Reset clears RTIE.
1 =
Real-time interrupts enabled.
0 =
Real-time interrupts disabled.
CTOFR — Core Timer Overow Flag Reset
Writing a logic one to this write only bit clears the CTOF bit. CTOFR always
reads as a logic zero. Reset does not affect CTOFR.
1 =
Clear CTOF ag bit.
0 =
No effect on CTOF ag bit.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CTSCR
R
CTOF
RTIF
CTOFE
RTIE
00
RT1
RT0
$0008
W
CTOFR
RTIFR
reset:
00000011
Figure 9-2. Core Timer Status and Control Register (CTSCR)
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