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參數(shù)資料
| 型號(hào)： | L84225 |
| 英文描述： | L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02 |
| 中文描述： | L84225 100BaseTX/FX/10BaseT物理層設(shè)備的技術(shù)手冊(cè)，4月2日 |
| 文件頁(yè)數(shù)： | 9/118頁(yè) |
| 文件大?。?/td> | 890K |
| 代理商： | L84225 |
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Pin Description
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
9 of 118
April, 2002
Miscellaneous
Pin #
Pin Name
I/O
Description
111
ANEG
I
AutoNegotiation Enable Input.
This digital input, ANDed with
register bit 0.12, enables AutoNegotiation for all channels.
1 = AutoNegotiation On & Combined with Speed and Duplex pins,
control advertisement. See
Table 1
for the different combinations.
0 = Off
120
119
113
112
SPEED_[3:0]
I
Speed Selection Input.
These digital inputs, ANDed with register
bit 0.13, select speed in each corresponding channel. Please refer
to
Table 1
for the different combinations.
1 = 100 Mbps Mode
0 = 10 Mbps Mode
103
104
105
106
DPLX_[3:0]
I
Duplex Selection Input.
These digital inputs, ORed with register
bit 0.8, select the duplex mode in EACH corresponding channel.
They control advertisement when ANEG is enabled. See
Table 1
for the different combinations.
1 = Full Duplex Mode
0 = Half Duplex Mode
102
REPEATER
I
Repeater Mode Enable Input.
This digital input, ORed with reg-
ister bit 17.14, enables repeater mode for ALL channels.
1 = Repeater Mode Enabled
0 = Normal Operation
101
RMII_EN
I
Reduced Pin Count MII Interface Enable.
1 = RMII Mode Enabled
0 = MII Enabled
17
AD_REV
I
Pullup
Address Reverse Input.
1 = Normal
In this mode, physical ports 0-3 are mapped to MI addresses 0-3
in the same order.
0 = Reverse Address Mode Select
In this mode, physical ports 0-3 are mapped to MI addresses 3-0
respectively. This is the reverse to the normal order.
118
CLKIN
I
Clock Input.
In MII mode, there must be a 25 MHz clock input to
this pin. In RMII mode, there must be a 50 MHz clock input to this
pin. TXCLK is generated from the input to this pin.
109
RESET
I
Pullup
Hardware Reset Input.
1 = Normal
0 = Device In Reset State
(Reset is complete 50 ms after RESET goes high).
Pin Description (Cont.)
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