- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367493 > L84225 L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02 PDF資料下載
參數(shù)資料
| 型號： | L84225 |
| 英文描述： | L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02 |
| 中文描述： | L84225 100BaseTX/FX/10BaseT物理層設(shè)備的技術(shù)手冊，4月2日 |
| 文件頁數(shù)： | 19/118頁 |
| 文件大?。?/td> | 890K |
| 代理商： | L84225 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁
Functional Description
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
19 of 118
April, 2002
The collision output, COL, is asserted whenever the collision condition is
detected.
2.2.3 MII - 10Mbps
10 Mbps operation is identical to the 100 Mbps operation, except:
TXCLK and RXCLK clock frequency is 2.5 MHz.
TXER is ignored.
RXER is disabled and always held low.
Receive operation is modified as follows. On the receive side, when
the squelch circuit determines that invalid data is present on the TP
(Twisted Pair) inputs, the receiver is idle. During idle, RXCLK follows
TXCLK, RXD[3:0] is held low, and CRS and RXDV are deasserted.
When a start of packet is detected on the TP receive inputs, CRS is
asserted and the clock recovery process starts on the incoming TP
input data. After the receive clock has been recovered from the data,
the RXCLK is switched over to the recovered clock output and the
data valid signal RXDV is asserted on a falling edge of RXCLK. Once
RXDV is asserted, valid data is clocked out on RXD[3:0] on falling
edges of the RXCLK clock. The RXD[3:0] data has the same packet
structure as the TXD[3:0] data and is formatted as specified in IEEE
802.3 and shown in
Figure 3
. When the end of packet is detected,
CRS and RXDV are deasserted. CRS and RXDV also stay
deasserted as long as the channel is in the Link Fail State.
2.2.4 RMII - 100 Mbps
The RMII is a reduced pin count version of the MII defined by an industry
group, the RMII Consortium. The RMII is a two-bit-wide packet data
interface that operates at 50 Mhz. The L84225 meets all the RMII
requirements outlined in the RMII Consortium specifications and can
directly connect to any Ethernet controller that also complies with the
RMII specifications.
The RMII is similar to the MII, except:
The data path is two bits wide instead of four.
Transmit and receive data is passed over TXD[1:0] and RXD[1:0]
pins, respectively.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| L84302 | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| L8560 | Low-Power SLIC with Ringing |
| L8567 | SLIC for Peoples Republic of China Applications |
| L8567-32PLCC | Telecommunication IC |
| L8567-44PLCC | Telecommunication IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| L84225/B1 | 制造商:LSI Corporation 功能描述: |
| L8446-04 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
| L8446-06 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
| L8446-07 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
| L8446-41 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。