參數(shù)資料
型號: L84225
英文描述: L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02
中文描述: L84225 100BaseTX/FX/10BaseT物理層設(shè)備的技術(shù)手冊,4月2日
文件頁數(shù): 49/118頁
文件大?。?/td> 890K
代理商: L84225
Functional Description
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
49 of 118
April, 2002
2.24 Repeater Mode
The L84225 has one predefined repeater mode which can be enabled
by asserting the REPEATER pin. When this mode is enabled, the device
operation is altered as follows:
TXEN to CRS loopback is disabled.
2.25 MI Serial Port
2.25.1 Signal Description
The MI serial port has five pins, MDC, MDIO, and PHYAD[4:2]. MDC is
the serial shift clock input. MDIO is a bidirectional data I/O pin.
PHYAD[4:2] are physical address pins.
Pins PHYAD[4:2] set the three most significant bits of the PHY address.
The two least significant bits of the PHY address are set internally to
match the channel number, as shown in
Table 6
.
Table 5
LED Event Definition
Symbol
Definition
ACT
Activity Occurred, Stretch Pulse to 100 ms
COL
Collision Occurred, Stretch Pulse to 100 ms
LINK100
100 Mb Link Detected
LINK10
10 Mb Link Detected
LINK
100 Mb or 10 Mb Link Detected
LINK+ACT
LED on if Link Detected (10 or 100). LED Blinks if Activity
Determined, Stretch Pulse to 100 ms
FDX
Full Duplex Mode Detected with Link Pass
10/100
10 Mb Mode Enabled (High) or 100 Mb Mode Enabled (Low)
with Link Pass
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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