參數(shù)資料
型號(hào): L84225
英文描述: L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02
中文描述: L84225 100BaseTX/FX/10BaseT物理層設(shè)備的技術(shù)手冊(cè),4月2日
文件頁(yè)數(shù): 55/118頁(yè)
文件大?。?/td> 890K
代理商: L84225
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Functional Description
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
55 of 118
April, 2002
registers contain an identification code unique to the L84225 and their bit
definition complies with the IEEE 802.3 specifications.
The structure and bit definition of the Auto Negotiation Advertisement
and Auto Negotiation Remote End Capability registers is shown in
Table 14
and
Table 15
, respectively. These registers are used by the Auto
Negotiation algorithm and their bit definition complies with the IEEE
802.3 specifications.
The Global Configuration Register, shown in
Table 16
, stores various
configuration inputs and is common for all four channels. This register is
reserved for factory use only.
The Channel Configuration Register, shown in
Table 17
, stores various
configuration inputs unique to each channel. This register is reserved for
factory use only.
The structure and bit definition of the Channel Status Output Register is
shown in
Table 18
. This register contains output status information from
each channel.
The structure and bit definition of the Global Interrupt Mask Register is
shown in
Table 19
. This register is common for all four channels. Bit 7 is
the interrupt indication. The 7 least significant bits are the Mask bits for
the R/LT status bits in the Channel Status Output Register.
Register 20 in
Table 20
is reserved for factory use only. All bits must be
set to the pre-set default states shown for normal operation.
2.25.7 Invalid Registers
The registers in locations 6-15 and 21-31 are not implemented on the
device and are therefore unused. When an unused register is read, the
value returned can be configured to be either all 0s or all 1s by
appropriately pinstrapping the REGDEF pin.
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參數(shù)描述
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