參數(shù)資料
型號: L84225
英文描述: L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02
中文描述: L84225 100BaseTX/FX/10BaseT物理層設備的技術手冊,4月2日
文件頁數(shù): 25/118頁
文件大?。?/td> 890K
代理商: L84225
Functional Description
Copyright 1999-2002 by LSI Logic Corporation. All rights reserved.
25 of 118
April, 2002
ESD, and codeword error bits in the MI serial port Channel Status Output
register.
2.4.2 Manchester Decoder - 10 Mbps
In Manchester coded data, the first half of the data bit contains the
complement of the data, and the second half of the data bit contains the
true data. The L84225 Manchester decoder converts the single data
stream from the TP receiver into NRZ data for the controller interface by
decoding the data and stripping off the SOI pulse. Since the clock and
data recovery block has already separated the clock and data from the
TP receiver, the Manchester decoding process to NRZ data is inherently
performed by that block.
2.4.3 Decoder Bypass
The 4B5B decoder can be bypassed by setting the bypass
encoder/decoder bit in the MI serial port Channel Configuration register.
When this bit is set to bypass the encoder/decoder:
5B code words are passed directly to the controller interface from the
descrambler without any alterations.
CRS is asserted whenever the device is in the Link Pass state.
2.5 Clock and Data Recovery
2.5.1 Clock Recovery - 100 Mbps
Clock recovery is done with a PLL. If there is no valid data present on
the receive inputs, the PLL is locked to the 25 MHz TXCLK. When valid
data is detected on the receive inputs with the squelch circuit and when
the adaptive equalizer has settled, the PLL input is switched to the
incoming data stream. The PLL then recovers a clock by locking onto the
transitions of the incoming signal. The recovered clock frequency is a 25
MHz nibble clock, and that clock is output as the controller interface
signal RXCLK.
For FX operation, when the SD pin is asserted, the PLL input is switched
to the incoming data on the input.
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相關代理商/技術參數(shù)
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